8T FinFET SRAM Cell Using Schmitt Trigger for Low-Voltage Read Stability
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Solution Overview
Problem
Conventional 6T SRAM cells experience read errors in low-voltage environments due to noise-induced voltage exceeding the trip voltage, leading to reliability issues and increased power consumption with larger transistor counts for improved designs like the 10T SRAM cell.
Innovation Solution
A Schmitt trigger-based FinFET SRAM cell is developed, reducing the number of transistors from 10T to 8T by utilizing two independent gates for each FinFET, effectively simplifying the circuit layout and reducing area, while maintaining performance by controlling conduction states with separate read/write control lines and bit lines to prevent read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a 6T SRAM cell is used, then the device complexity is low, but read stability deteriorates in low-voltage environments due to noise-induced voltage exceeding the trip voltage
Solution Approach 1:
The patent divides the control function into separate read control and write control pathways. The read control path includes additional transistors (third and fourth pass transistors) that are independent from the write control path, allowing read operations to be performed without activating the write control transistors, thus preventing write disturbances during read operations and improving read stability.
Solution Approach 2:
The patent introduces intermediate control transistors (third and fourth pass transistors) that act as mediators between the bit lines and the storage nodes during read operations. These intermediate transistors enable controlled access to storage nodes while isolating the main write control transistors, preventing noise propagation and ensuring stable read operations at low voltages.
2Reliability
If a 10T SRAM cell is used to improve read stability, then read stability improves, but device complexity and power consumption increase
Solution Approach 1:
The patent makes the first and second pass transistors serve dual functions: they act as write control transistors when activated by the write control signal, and they serve as part of the read control path when the third and fourth pass transistors are activated. This multi-functionality reduces the need for completely separate read and write control circuits, thereby reducing overall transistor count while maintaining read stability.
Solution Approach 2:
The patent merges the read control and write control functions into a unified control structure where the first and second pass transistors participate in both read and write operations depending on the control signals. The third and fourth pass transistors are integrated into the existing structure rather than being completely separate, reducing total transistor count while preserving the ability to perform stable read operations.
3Area of moving object
If MOSFET size is reduced to increase chip density, then chip density improves, but variance and uncertainty of MOSFET properties increase
Solution Approach 1:
The patent applies different control strategies to different parts of the SRAM cell. The FinFET structure provides enhanced local control over the channel, and the separate read/write control transistors provide localized control over specific access paths. This local quality approach allows optimization of specific regions for their particular functions while accommodating the variability of miniaturized MOSFETs through targeted control rather than requiring uniform performance across all components.
Data Source
AI summary
The present invention provides a Schmitt trigger-based FinFET static random access memory (SRAM) cell, which is an 8-FinFET structure. A FinFET has the functions of two independent gates. The new SRAM cell uses only 8 FinFET per cell, compared with the 10-FinFET structure in previous works. As a result, the cell structure of the present invention can save chip area and raise chip density. Furthermore, this new SRAM cell can effectively solve the conventional problem that the 6T SRAM cell is likely to have read errors at a low operating voltage.