8T SRAM Cell Clock Segmentation for Two-Port Read Write
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Solution Overview
Problem
Current memory architectures face performance limitations and potential functional failures when attempting simultaneous read and write operations on the same bit cell, particularly due to timing mismatches and sensitivity to low operating voltages, which restrict two-port functionality and lead to yield loss.
Innovation Solution
The proposed solution involves performing read operations in the positive portion of a clock cycle and write operations in the negative portion, with write precharge during read operations and read precharge during write operations, using an 8T memory bit cell with an inverter to invert the clock signal and apply it to the write address flip-flop/clock circuit, allowing for loose self-timing to manage clock cycle states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential rising and falling edges of the clock are used for two-port functionality, then twice the cycle time of a single-port memory is achieved, but timing mismatches and lower operating voltages limit performance
Solution Approach 1:
The patent segments the clock cycle into distinct phases (first clock edge for read, second clock edge for write) and uses separate word lines (first word line for read, second word line for write) controlled by different clock edges. This segmentation allows independent optimization of read and write operations, achieving twice the cycle time while maintaining reliability through phased execution rather than simultaneous operation.
Solution Approach 2:
The patent employs periodic action by using alternating clock edges (rising edge, falling edge) to sequentially enable read and write operations. Each clock cycle provides a periodic opportunity for both operations, with the first edge dedicating to read and the second edge to write, thereby achieving doubled productivity while avoiding timing mismatches through regular, predictable timing.
2Productivity
If asynchronous feature is employed for two-port functionality, then two-port operation in a given clock cycle is achieved, but the memory is prone to timing mismatches resulting in yield loss
Solution Approach 1:
The patent introduces feedback mechanisms through clock edge detection and control logic that monitors the timing and sequencing of read and write operations. The control circuitry uses feedback from clock edges to coordinate word line activation, ensuring proper timing relationships and preventing timing mismatches that would otherwise cause yield loss while maintaining high-speed two-port operation.
Solution Approach 2:
The patent applies preliminary action by preparing and precharging word lines and bit lines before actual read or write operations occur. The first word line is activated on the first clock edge before the second word line is activated on the second clock edge, ensuring that read operations are fully prepared and stabilized before write operations begin, thereby preventing timing conflicts and improving yield.
3Reliability
If 8T bit cell with both single port and two port functionality is used, then robust high performance is achieved, but simultaneous read and write operations on the same bit cell cannot be achieved and potential errors occur when accessing the same row
Solution Approach 1:
The patent applies local quality by creating spatial and functional separation within the bit cell structure. Different regions of the circuit (first word line controlled region, second word line controlled region) have specialized functions optimized for their specific operations. This local differentiation allows the same physical bit cell to support both read and write operations with distinct control mechanisms, achieving versatility while maintaining robustness through localized optimization.
Data Source
AI summary
An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.