8T SRAM Layout With Counter Doping for Threshold Voltage Balance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The performance of eight-transistor SRAM cells is deteriorated due to unbalanced gate electrode layers, leading to lower operation speed, reduced device reliability, and higher working voltage, as well as increased power consumption.
Innovation Solution
A counter doping process is implemented to balance the threshold voltages of transistors in the read-port and write-port portions of the SRAM cell by selectively doping impurities in specific regions, reducing the difference in threshold voltages between pull-down transistors and adjusting the work function levels of gate electrode layers to achieve symmetric configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If gate electrodes are extended from write-port to read-port in asymmetric configuration, then device integration is achieved, but SRAM performance deteriorates due to unbalanced gate electrode layers
Solution Approach 1:
The patent applies asymmetry principle by intentionally creating different gate electrode layer configurations for write-port and read-port portions. Specifically, the first gate electrode layer is formed only over write-port transistors while the second gate electrode layer is formed only over read-port transistors, resulting in asymmetric structures that are optimized for their respective functions rather than forcing symmetric extension of gate electrodes across the entire cell.
Solution Approach 2:
The patent implements local quality by providing different gate electrode structures in different regions of the SRAM cell. The write-port portion receives a first gate electrode layer with specific properties while the read-port portion receives a second gate electrode layer with different properties, allowing each region to have the optimal structure for its specific function.
2Ease of manufacture
If asymmetric gate electrode configuration is used, then manufacturing simplicity is maintained, but operation speed decreases
Solution Approach 1:
The patent applies segmentation by dividing the gate electrode structure into separate first and second gate electrode layers that are formed independently over different transistor portions. This segmentation allows each gate electrode layer to be optimized for its specific region (write-port or read-port) while maintaining manufacturing simplicity through sequential formation processes.
3Device complexity
If unbalanced gate electrode layers are present, then device structure is simplified, but threshold voltage balance between pull-down transistors deteriorates
Solution Approach 1:
The patent applies parameter changes by modifying the gate electrode layer parameters (presence, thickness, material composition) differently for write-port and read-port portions. The first gate electrode layer is formed with specific parameters over write-port transistors while the second gate electrode layer is formed with different parameters over read-port transistors, allowing precise control of threshold voltages to achieve balance between pull-down transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the minimum operating voltage (Vccmin) by 55-60 mV, improves the balance of threshold voltages, and enhances the overall performance of the SRAM cell by mitigating the adverse effects of asymmetric gate electrode configurations.
Implementation Method 1
A counter doping process is implemented to balance the threshold voltages of transistors in the read-port and write-port portions of the SRAM cell by selectively doping impurities in specific regions
Data Source
AI summary
A static random access memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.