8T SRAM Circuit for Parallel In-Memory Computing
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Solution Overview
Problem
Existing memory circuit and cell array designs, such as 8T 2P-SRAM and special 6T SP-SRAM, require complex manufacturing processes and cannot provide parallel in-memory computing functions, leading to increased design and manufacturing difficulties.
Innovation Solution
An in-memory computing (IMC) circuit structure based on eight-transistor static random access memory (8T SRAM) is introduced, featuring four bit lines, two word lines, and a direction configuration circuit, allowing for parallel IMC functions by enabling simultaneous data processing and logic operations across multiple rows of the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If special 6T SP-SRAM or 8T 2P-SRAM is used for IMC, then in-memory computing function is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies universality by designing the 8T SRAM cell to perform both traditional memory storage functions and in-memory computing functions through the same hardware structure. The circuit can operate as a standard 8T 2P-SRAM for data storage while also performing logic operations (AND, OR, NAND, NOR) directly within the memory cell, eliminating the need for specialized 6T SP-SRAM structures with additional Vt setting layers and shielding layers.
2Adaptability or versatility
If special 6T SP-SRAM is used for IMC, then in-memory computing function is achieved, but design complexity increases
Solution Approach 1:
The patent applies universality by designing the 8T SRAM cell to perform both traditional memory storage functions and in-memory computing functions through the same hardware structure. The circuit can operate as a standard 8T 2P-SRAM for data storage while also performing logic operations (AND, OR, NAND, NOR) directly within the memory cell, eliminating the need for specialized 6T SP-SRAM structures with additional Vt setting layers and shielding layers.
3Ease of operation
If sequential data processing is used, then data is processed step-by-step, but waiting time and power consumption increase
Solution Approach 1:
The patent applies self-service by enabling the memory cell to automatically perform logic operations on stored data without requiring external processing. The in-memory computing capability allows the SRAM cell to execute Boolean operations (AND, OR, NAND, NOR) directly on the data held in its storage nodes, eliminating the need to transfer data to separate processing units and reducing waiting time and power consumption.
4Productivity
If multiple delay cycles are used for computation, then computation is performed externally, but power consumption and waiting time increase
Solution Approach 1:
The patent applies self-service by enabling the memory cell to automatically perform logic operations on stored data without requiring external processing. The in-memory computing capability allows the SRAM cell to execute Boolean operations (AND, OR, NAND, NOR) directly on the data held in its storage nodes, eliminating the need to transfer data to separate processing units and reducing waiting time and power consumption.
Data Source
AI summary
The present disclosure relates to a circuit structure for in-memory computing. The circuit structure comprises a plurality of 8T SRAMs, four BLs, two WLs, and a direction configuration circuit. Each of the 8T SRAMs comprises two groups of read/write dual ports, two WL ports and two direction configuration ports. Data of first read/write port and second read/write port of each group of the read/write dual ports are inverse of each other. Each of the BLs is connected to a corresponding processor, and is connected to a read/write port of a corresponding read/write dual port of each 8T SRAM in a row direction or a column direction. Each of the WLs is connected to a corresponding processor and connected to a corresponding WL port of each 8T SRAM.