8T SRAM Compute-in-Memory With Isolated Read Bit-Lines
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Solution Overview
Problem
Existing compute-in-memory systems face instability issues when multiple word lines are activated simultaneously, leading to bit cell state flipping and significant area overhead due to intermediate storage needs, which limits their effectiveness in multi-bit computations.
Innovation Solution
The implementation of an 8T SRAM cell with a decoupled read bit-line (RBL) and write bit-line (WBL) structure, allowing multiple read word lines to be activated without upsetting storage node voltage, and using multi-bit weight capacitors for charge sharing to perform multiply-accumulate operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple word lines are activated simultaneously in existing compute-in-memory systems, then computation speed is improved, but bit cell state stability deteriorates causing state flipping
Solution Approach 1:
The bit line is segmented into a read bit line (RBL) and a write bit line (WBL), which are physically isolated from each other. This segmentation allows the read operation to occur on the RBL while the write operation occurs on the WBL, preventing the write operation from interfering with the stored data on the storage nodes. This resolves the contradiction by enabling simultaneous word line activation for computation while maintaining bit cell state stability through physical isolation of read and write paths.
2Measurement precision
If intermediate storage is used for multi-bit computations, then computation accuracy is improved, but area overhead increases significantly
Solution Approach 1:
The patent merges the computation function with the memory storage function by performing multiply-accumulate operations directly within the memory array. The read bit line serves dual purposes: it reads the stored data and simultaneously accumulates the weighted sums during the read operation. This eliminates the need for separate intermediate storage structures, achieving both computation accuracy and reduced area overhead by combining storage and computation in the same physical location.
Solution Approach 2:
The memory cell and its associated bit lines are designed to perform multiple functions: data storage, data reading, and in-memory computation. The read bit line universally serves as both a data output line and an accumulation line for multi-bit computations, eliminating the need for dedicated intermediate storage structures. This multi-functionality resolves the contradiction by achieving computation accuracy through the same structure used for storage, thereby reducing area overhead.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables stable multi-bit compute-in-memory operations without intermediate storage, allowing for faster and more efficient processing of inputs weighted by multi-bit weights, improving computation speed and reducing area overhead.
Implementation Method 1
the significance factor corresponding to the weight bit being represented by the output line is stored in the capacitor
Implementation Method 2
the read port adapted to, upon an activation signal at the read-enable input, generate at the output a signal indicative of the signal stored at the node in the memory unit and isolate the output line from the node
Data Source
AI summary
An example computing device includes an array of memory cells, such as 8-transistor SRAM cells, where the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, where the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. A method of making a computing device as described is also disclosed.