8T SRAM Leakage Power Reduction via Dynamic Bitline Control
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Solution Overview
Problem
Conventional 8T SRAM cells suffer from high leakage currents and power wastage due to precharge transistors always being turned on during inactive or standby modes, leading to performance degradation and increased power consumption.
Innovation Solution
The method involves dynamically placing 8T SRAM cells in a reduced power state by allowing read and write bitlines to float during inactive states and precharging them only during access operations, eliminating the need for precharge transistors and thereby eliminating leakage paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If precharge transistors are always turned on in 8T SRAM cells during inactive states, then bitlines are precharged and ready for access operations, but leakage current increases and power consumption rises
Solution Approach 1:
The patent applies dynamics by transitioning the bitline precharge state from static (always on) to dynamic (conditionally activated). The precharge transistors are controlled by control signals that enable them to be turned on only when needed for access operations, and turned off during inactive states. This dynamic control eliminates continuous leakage paths while maintaining readiness when required.
Solution Approach 2:
The patent changes the operational parameter of precharge transistors from a fixed on-state to a variable state controlled by control signals. By modifying the gate control mechanism, the transistors can dynamically adjust their conductivity based on operational requirements, reducing leakage current during inactive periods while ensuring proper precharging during access operations.
2Area of moving object
If device sizes are shrunk in nanometer technologies, then integration density increases, but performance targets become harder to meet due to random doping fluctuations and low operating voltages
Solution Approach 1:
The patent segments the SRAM cell architecture by adding separate precharge transistors and control mechanisms. This segmentation allows independent control of precharge operations, enabling the cell to maintain stable operation at smaller sizes by isolating the precharge function from the storage function. The segmented architecture compensates for the effects of random doping fluctuations and low operating voltages.
Solution Approach 2:
The patent introduces control signals as intermediaries between the precharge transistors and the bitlines. These control signals mediate the precharge operation, allowing precise timing and duration control. This intermediary mechanism enables the smaller devices to achieve reliable precharging despite reduced margins from shrinking dimensions and lower operating voltages.
3Productivity
If 8T SRAM cell configuration is used instead of 6T, then performance during read access operations improves, but leakage current becomes much higher due to additional leakage paths
Solution Approach 1:
The patent applies dynamics by making the precharge transistors controllable rather than permanently conductive. The separate precharge transistors with control signals enable the 8T cell to maintain its read performance benefits while dynamically eliminating leakage paths during inactive states. This dynamic control resolves the contradiction between improved read performance and reduced leakage current.
Data Source
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AI summary
Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.