8T SRAM Cell With Separate Pass Gates for Low-Voltage Operation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional 6T SRAM cells face challenges in scaling supply voltage due to read and write signal margin requirements, particularly in FinFET CMOS processes, leading to increased complexity and size when additional bit lines and transistors are added to improve margins.
Innovation Solution
An 8T SRAM cell design with separate pass transistors for read and write operations, using a single pair of bit lines and an elevated memory supply voltage (VDDM) for write circuitry but not read circuitry, along with an additional word line for control, decouples read and write margins and improves signal margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional bit lines and read transistors are added to improve read and write margins, then signal margins are improved, but cell size and complexity increase
Solution Approach 1:
The patent merges read and write operations to share the same bit lines (BL and BLB), eliminating the need for separate read and write bit lines. The cross-coupled latch structure integrates both read and write functionality into a unified circuit, reducing overall cell complexity while maintaining adequate signal margins through the shared bit line architecture.
Solution Approach 2:
The bit lines serve dual purposes: they are used for both read operations (sensing data from the latch) and write operations (forcing data into the latch). This multi-functionality eliminates the need for dedicated read and write bit lines, reducing cell complexity while maintaining reliable signal margins through proper timing control of the word line and bit line precharging.
2Area of stationary object
If traditional 6T SRAM cell is used, then cell size is small, but supply voltage scaling is difficult due to margin requirements
Solution Approach 1:
The patent segments the pass transistor functionality into separate read pass transistor (connected to BL) and write pass transistor (connected to BLB), each optimized for its specific operation. This segmentation allows independent optimization of read and write margins, enabling better supply voltage scaling capability while maintaining a compact cell structure through the shared bit line architecture.
Solution Approach 2:
The patent applies different transistor types locally: n-channel transistors are used for the latch and read pass transistor where high electron mobility is beneficial, while p-channel transistors are used for the write pass transistor where hole mobility characteristics are advantageous. This local quality differentiation optimizes performance for each specific function, improving supply voltage scaling capability without significantly increasing cell size.
3Reliability
If separate read and write bit lines are used, then read and write margins are improved, but cell area increases
Solution Approach 1:
The patent merges the read and write bit lines into a single shared pair of bit lines (BL and BLB). The cross-coupled latch structure enables both read and write operations to occur on the same bit lines through proper timing control, significantly reducing cell area while maintaining adequate margins through the inherent regenerative feedback of the latch.
Solution Approach 2:
The patent uses periodic timing control of the word line (WL) to alternately enable read and write operations on the shared bit lines. During write operations, WL is high to enable the write pass transistor; during read operations, WL is low to enable the read pass transistor. This periodic switching allows efficient time-division multiplexing of the shared bit lines, maintaining signal margins through proper timing while minimizing cell area.
Data Source
AI summary
An eight-transistor (8T) Static Random-Access Memory (SRAM) cell has four latch transistors, and pairs of n-channel and p-channel pass transistors in parallel to only one pair of bit lines. During read, only the read word line and the n-channel pass transistors are activated, but during a write both the read word line and an extra write word line are activated to turn on all four pass transistors. The cell is powered by VDDM, one threshold above the normal VDD power supply of the read sense and write drivers and interfaces. The bit lines are precharged to VDD but pulled up to VDDM by a latch of cross-coupled p-channel transistors. Any p-channel transistors that connect to the bit lines are driven inactive by VDDM. The read margin is largely decoupled from the write margin by two additional p-channel pass transistors and one extra word line versus a standard 6T cell.