8T SRAM Compute-in-Memory With Stable Multi-Row Weighted Sums
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing compute-in-memory systems face challenges with stability when performing multi-bit operations, as multiple word lines activated simultaneously can upset the stability of memory cells, and they require significant area overhead for intermediate calculations, making them inefficient for complex computations.
Innovation Solution
The implementation of an 8T SRAM cell with a decoupled read bit-line (RBL) and write bit-line (WBL) structure, allowing multiple read word lines to be activated simultaneously without upsetting storage node voltage, and using multi-bit weight capacitors for proportional charge sharing to perform multiply-accumulate operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple word lines are activated simultaneously for multi-bit operations, then computation speed is improved, but stability of memory cells deteriorates
Solution Approach 1:
The bit lines are segmented into separate read bit lines (RBL) and write bit lines (WBL), with corresponding separate word lines (RWL and WWL). This segmentation allows read operations to be performed simultaneously without interfering with the stability of storage nodes during write operations, resolving the contradiction between computation speed and memory cell stability.
2Measurement precision
If intermediate storage is added for multi-bit operations, then computation accuracy is improved, but area overhead increases
Solution Approach 1:
The read port functionality is merged directly into the memory cell structure, eliminating the need for separate intermediate storage elements. The read transistor and read bit line are integrated with each memory cell, allowing multi-bit operations to be performed directly on stored data without requiring additional area for intermediate storage, thus maintaining computation accuracy while reducing area overhead.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables stable multi-bit compute-in-memory operations without intermediate storage, improving computation speed and efficiency by allowing simultaneous activation of read word lines and accurate representation of weighted sums through analog-to-digital conversion.
Implementation Method 1
an output interface configured to permit the capacitors to share charge stored on them
Data Source
AI summary
A computing device in some examples includes an array of memory cells, such as 8-transistor SRAM cells, in which the read bit-lines are isolated from the nodes storing the memory states such that simultaneous read activation of memory cells sharing a respective read bit-line would not upset the memory state of any of the memory cells. The computing device also includes an output interface having capacitors connected to respective read bit-lines and have capacitance that differ, such as by factors of powers of 2, from each other. The output interface is configured to charge or discharge the capacitors from the respective read bit-lines and to permit the capacitors to share charge with each other to generate an analog output signal, in which the signal from each read bit-line is weighted by the capacitance of the capacitor connected to the read bit-line. The computing device can be used to compute, for example, sum of input weighted by multi-bit weights.