8T SRAM Cell With Write-Enhance Pass Gates for Faster Writes
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Solution Overview
Problem
Existing semiconductor devices and methods for fabricating ICs face challenges in scaling down while maintaining efficiency and cost-effectiveness, particularly in enhancing write ability and speed in SRAM bit cells without compromising data stability.
Innovation Solution
The implementation of a single-port, 8T SRAM cell with write enhance pass gate transistors, where two write enhance pass gate transistors are parallelly connected with pass gate transistors in a standard 6T SRAM cell, allowing independent control using a write enhance word line to optimize pass gate strength during read/write operations, utilizing stacked complementary FETs to enhance write ability and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If two write enhance pass gate transistors are parallelly connected with pass gate transistors in a standard 6T SRAM cell, then write ability and speed are enhanced, but device complexity increases
Solution Approach 1:
The pass gate function is segmented into two independent components: standard pass gate transistors (PGT) and write enhance pass gate transistors (WPGT). This segmentation allows each transistor type to be independently controlled via separate word lines (WL and WWL), enabling optimized write speed through coordinated activation while maintaining manageable device complexity through modular control architecture.
2Adaptability or versatility
If write enhance pass gate transistors are independently controlled using a write enhance word line, then pass gate strength can be optimized during read/write operations, but device complexity increases
Solution Approach 1:
The pass gate strength is made dynamic through independent control of PGT and WPGT via separate word lines. During write operations, both word lines can be activated to maximize pass gate strength for enhanced write ability. During read operations, only the standard word line is activated to maintain normal read functionality. This dynamic adaptability allows optimization of performance characteristics without requiring complex additional control circuitry.
3Reliability
If the SRAM cell configuration is expanded from 6T to 8T, then write ability is enhanced, but the area of the device increases
Solution Approach 1:
The write enhance pass gate transistors are merged in parallel with the standard pass gate transistors, sharing common source and drain connections to the storage nodes. This merging approach allows the 8T configuration to achieve enhanced write ability through additional current paths while minimizing area increase by reusing existing transistor locations and interconnect structures, rather than adding completely separate components.
Data Source
AI summary
Embodiments of the present disclosure relate to a SRAM (static random access memory) bit cell. More particularly, embodiments of the present disclosure relate to a single port, 8T SRAM cell with write enhance pass gate transistors. Particularly, two write enhance pass gate transistors are parallelly connected with the pass gate transistors in a standard 6T SRAM cell. The write enhance pass gate transistors are independently controlled from the pass gate transistor using a write enhance word line. In some embodiments, the single port, 8T SRAM cell according to the present disclosure may be implemented by stacked complementary FETs. Empty or dummy PMOS transistors in a standard 6T stacked CFET SRAM cell are used as pass gate transistors or write enhance pass gate transistors.