9T SRAM Cell Architecture for In-Memory XOR and Secure Erasure
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Solution Overview
Problem
Existing static random-access memory (SRAM) technologies face challenges in performing XOR operations efficiently and securely, with issues such as data imprinting and data remanence, which can expose sensitive information to malicious retrieval and compromise security.
Innovation Solution
A 9T SRAM cell architecture is introduced, featuring multiple word lines, bit lines, and a reset bit line, allowing for conditional logic operations like XOR, data toggling, and secure erasure within the memory cell, utilizing enhanced transistor configurations for improved control and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SRAM architecture is used, then device complexity is reduced, but security is compromised due to data imprinting and data remanence vulnerabilities
Solution Approach 1:
The SRAM cell is segmented into multiple transistor components (9 transistors total) with distinct functional roles: access transistors (M1, M2), storage transistors (M3-M6), and control transistors (M7-M9). This segmentation allows independent control of read/write operations, data storage, and security functions, enabling secure data erasure while maintaining operational reliability
Solution Approach 2:
Control transistors M7, M8, and M9 serve as intermediary elements between the data storage nodes and the bit lines. These transistors act as gates that can selectively isolate the storage nodes from external access, preventing unauthorized reading or imprinting while allowing legitimate operations, thus providing a security layer without fundamentally changing the SRAM architecture
2Reliability
If XOR operations are performed individually on SRAM cells, then security is improved, but productivity decreases due to inability to batch process multiple rows
Solution Approach 1:
The control transistors M7, M8, and M9 provide multi-functionality by enabling both individual cell operations and batch array-level operations. By controlling these transistors, the system can perform XOR operations on single cells for security-critical data or across entire rows for bulk data processing, achieving both security and productivity
Solution Approach 2:
The invention extends XOR operation capability from the cell level (0D) to the array level (2D) by utilizing the control transistors as additional control dimensions. This allows simultaneous activation of multiple cells across different rows and columns, enabling batch processing while maintaining the security benefits of in-memory XOR operations
3Use of energy by moving object
If data is stored in traditional SRAM, then energy efficiency is improved with low power and refresh requirements, but security is compromised due to data remanence allowing malicious retrieval
Solution Approach 1:
The control transistors M7, M8, and M9 enable preliminary action by allowing the system to proactively erase data from storage nodes before potential security threats can exploit data remanence. The secure erase function can be activated whenever security concerns arise, preventing malicious retrieval while maintaining the low-power characteristics of SRAM during normal operation
Solution Approach 2:
The invention converts the harmful effect of data remanence into a benefit by using the same SRAM physical architecture that enables low-power operation. The control transistors allow selective isolation and erasure of data, turning the persistent nature of SRAM storage from a security vulnerability into a feature where data can be retained during normal operation but selectively erased when needed, all while maintaining energy efficiency
Data Source
AI summary
Provided is a memory circuit including a pair of cross-coupled inverters, the pair of cross-coupled inverters accessible by bit lines, wherein the access of the bit lines to the pair of cross-coupled inverters is controlled by access transistors, the access transistors controlled by a word line, and a dynamic node between one of the access transistors and one of the bit lines, the dynamic node storing a bit value.