O-RAN Accelerator Adaptation Layer Queue Assignment

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Solution Overview

Problem

Current O-RAN systems lack defined queue assignments for O-RAN AAL hardware based accelerators, limiting the potential utilization of inline AAL hardware and requiring vendors to define data assignment between physical layer 1 software and hardware accelerators without standardized guidelines.

Innovation Solution

The proposed solution involves defining specific queue assignments for different data types between physical layer 1 software and vendor hardware accelerators within the O-RAN AAL API specifications, utilizing predefined messaging characteristics to map messages to appropriate hardware accelerator queues, such as those associated with uplink and downlink messaging, cell-specific messaging, and sub-interface types.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If generic queue definitions are used in O-RAN AAL specifications, then vendor flexibility and implementation freedom are improved, but system performance optimization and standardized efficient data exchange are worsened

Engineering Contradiction:
Improvevendor flexibilityVSAvoiddata exchange efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies parameter changes by transitioning from generic queue definitions to specific queue assignments with defined messaging characteristics. The O-RAN AAL specifications are enhanced with concrete parameters including queue types (uplink, downlink, cell-specific, sub-interface), data types, and messaging patterns, enabling optimized hardware accelerator utilization while maintaining vendor implementation freedom through standardized guidelines.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If no standardized queue assignments are defined, then vendor implementation freedom is improved, but hardware accelerator utilization and system performance are worsened

Engineering Contradiction:
Improveimplementation freedomVSAvoidhardware utilization
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The patent implements universality by creating a comprehensive queue assignment framework that serves multiple functions simultaneously: it provides standardized guidelines for hardware accelerator utilization, defines messaging characteristics for different queue types, maintains vendor implementation freedom through optional adoption, and enables optimized data exchange patterns. This multi-functional approach resolves the contradiction between standardization and flexibility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If multiple possible queue assignments are allowed, then adaptability to different scenarios is improved, but system complexity and implementation difficulty increase

Engineering Contradiction:
Improvescenario adaptabilityVSAvoidimplementation complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the queue assignment space into distinct, well-defined categories: uplink queues, downlink queues, cell-specific queues, and sub-interface queues. Each segment has specific messaging characteristics and assignment rules, reducing implementation complexity while maintaining adaptability to different scenarios through the modular nature of these segmented definitions.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240045744A1Accelerator adapation layer (AAL) profile queues for inline acceleration of layer 1
Publication Date: 2024.02.08 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US20240045744A1 patent drawing
  • US20240045744A1 patent drawing
  • US20240045744A1 patent drawing

AI summary

A method, system and apparatus are disclosed. According to one or more embodiments, a node for managing data exchange between a first communication layer-second communication layer interface and a plurality of hardware accelerator queues is provided. The first layer is different from the second communication layer. The node including processing circuitry configured to: receive a first messaging from the first communication layer-second communication layer interface, determine that the first messaging is associated with at least one predefined messaging characteristic, and communicate the first messaging to a first hardware accelerator queue of the plurality of hardware accelerator queues based on the at least one predefined messaging characteristic of the first messaging.