AAO Semiconductor Structure for Low-Chip Dicing Lanes
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Solution Overview
Problem
Existing semiconductor fabrication methods using AAO embedded structures face issues with top side chipping and mechanical weakness of the die due to dicing techniques like DBG and LG-DBG, which are not effectively addressed by current dicing methods.
Innovation Solution
A method involving the formation of AAO embedded circuitry with controlled porous structures and MIM stacks, where the dicing area is treated differently to reduce chipping and enhance mechanical strength, using anodization and masking to control pore formation and fill only functional pores with MIM stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If dicing before grinding (DBG) is used to separate dies, then mechanical stress is improved and backside chipping is reduced, but topside chipping increases
Solution Approach 1:
The patent applies preliminary action by forming a relief groove along the dicing lane before the dicing process. This groove is created in advance to modify the stress distribution during subsequent dicing operations, preventing topside chipping while maintaining the mechanical stress benefits of DBG technique.
Solution Approach 2:
The relief groove acts as an intermediary structure between the dicing blade and the die edge. It modifies the interaction by providing a controlled stress relief path, preventing direct transmission of cutting forces that cause topside chipping while preserving the overall mechanical integrity achieved by DBG.
2Object-generated harmful factors
If laser grooving (LG) followed by grinding is used for dicing, then backside and topside chipping are reduced, but mechanical strength of the die is weakened
Solution Approach 1:
The patent replaces the thermal-mechanical laser grooving process with a purely mechanical relief groove formation process. This substitution eliminates the melting and structural damage caused by laser energy while still achieving the chipping prevention function through controlled mechanical stress modification.
Solution Approach 2:
The relief groove is a sacrificial, temporary structure created specifically for the dicing process. It serves its protective function during cutting and can be removed or integrated into the final structure, providing a low-cost solution that doesn't compromise the permanent mechanical strength of the die.
3Reliability
If AAO regions are formed along dicing areas to protect circuit areas from humidity, then leakage protection is improved, but dicing quality deteriorates due to chipping
Solution Approach 1:
The patent segments the AAO structure into two distinct regions: functional AAO regions within the circuit area that provide leakage protection, and a separate relief groove structure in the dicing area that prevents chipping. This segmentation allows each region to perform its specific function without interfering with the other.
Solution Approach 2:
The patent applies local quality by giving different structural characteristics to different areas of the wafer. The circuit area retains the dense AAO structure for humidity protection, while the dicing area features the relief groove geometry optimized for stress management during cutting, allowing each zone to have the properties needed for its specific function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in semiconductor structures with improved mechanical profiles, reduced delamination, chipping, and substrate cracking, while maintaining protection against humidity and leakage.
Implementation Method 1
The anodization converts the aluminium layer into AAO
Implementation Method 2
The anodization converts the aluminium layer into AAO
Implementation Method 3
the laser grooving results in some melting of the edge AAO region
Implementation Method 4
the laser grooving results in some melting of the edge AAO region
Data Source
Figure 1~3
Figure 4A~4C
Figure 4D~4F
AI summary
A method of fabricating a semiconductor structure is disclosed. The method comprises: forming a first metal layer over a wafer; forming a second metal layer over the first metal layer; forming a first porous structure in a first region of the second metal layer located above a circuit area of the wafer and a second porous structure in a second region of the second metal layer located above a dicing area of the wafer, wherein the first porous structure includes a first set of pores, and wherein the second porous structure includes a second set of pores; forming a metal-insulator-metal stack in the first set of pores of the first porous structure; and etching the second set of pores of the second porous structure to expose the dicing area of the silicon wafer.