ABB Chipset JTAG Memory Test Architecture for Low-Pin Defect Detection
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Solution Overview
Problem
Conventional test methods for analog base-band (ABB) chipsets in mobile communication systems face limitations in lab and automatic test equipment (ATE) environments due to high costs and complexity, making it difficult to satisfy various test modes and predict defects, leading to inefficiencies and increased costs.
Innovation Solution
The ABB chipset is enhanced with an internal serial interface, memory, and a Joint Test Action Group (JTAG) interface, allowing for internal test pattern storage and control, reducing the number of external pins and enabling testing in both lab and ATE environments by applying test modes and control signals through a JTAG program.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ATE test environment is used for testing ABB chipset, then test accuracy and performance are improved, but test cost and device complexity are increased
Solution Approach 1:
The patent combines ATE test environment capabilities with lab test environment simplicity by integrating a JTAG interface and internal memory directly into the ABB chipset. This merging allows the chipset to perform self-testing with ATE-level accuracy while eliminating the need for complex external testing equipment, thus reducing overall device complexity and test cost.
Solution Approach 2:
The ABB chipset is equipped with an internal memory and JTAG interface that enable it to store and execute test patterns autonomously. This self-service capability allows the chipset to perform comprehensive tests without requiring complex external ATE equipment, thereby maintaining high test accuracy while reducing device complexity and testing cost.
2Reliability
If various test patterns are applied to ABB chipset, then defect detection capability is improved, but number of pins and device complexity are increased
Solution Approach 1:
The patent merges multiple test pattern storage and control functions into a single internal memory unit within the ABB chipset. This internal memory can store various test patterns (e.g., PRBS, sine wave, square wave) and work cooperatively with the JTAG interface, eliminating the need for multiple external pins while maintaining enhanced defect detection capability across different test modes.
Solution Approach 2:
The internal memory and JTAG interface combination serves multiple functions: storing various test patterns, controlling test sequence execution, and facilitating data output. This multi-functional design enables comprehensive defect detection without requiring separate dedicated pins for each test function, thus reducing overall pin count while improving reliability.
3Adaptability or versatility
If JTAG interface and internal memory are added to ABB chipset, then testing capability in lab environment is improved, but device complexity is increased
Solution Approach 1:
The patent merges the JTAG interface and internal memory into an integrated testing subsystem within the ABB chipset. This combination provides ATE-level testing capability in lab environments by enabling the chipset to autonomously store, execute, and report test results, while the integrated design minimizes the increase in overall device complexity compared to having separate external testing components.
Data Source
AI summary
An analog base-band (ABB) chipset of a mobile communication system comprises a memory configured to store a test pattern, a test control unit configured to generate a control signal during a test mode, an ABB unit configured to perform a test operation by receiving the test pattern from the memory in response to the test control signal and to output data of the test pattern to the memory in response to the test control signal, and a path selection circuit configured to form a flow path of the test pattern in the ABB unit in response to the test control signal.