ABF Package Substrate Structure for Fine-Line Semiconductor Packaging
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Solution Overview
Problem
Conventional semiconductor packaging methods face challenges such as increased manufacturing difficulty and cost due to the use of through-silicon interposers, poor conductive and heat dissipation performance, and thermal stress issues, which hinder miniaturization and reliability.
Innovation Solution
The use of an Ajinomoto build-up film (ABF) as an insulating layer in a package substrate with distinct dielectric layers for signal transmission, eliminating the need for through-silicon interposers and C4 conductive elements, and optimizing thermal stress distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon interposer is used as signal transmission medium, then signal transmission between chip and circuit board is achieved, but manufacturing process difficulty and cost increase greatly
Solution Approach 1:
The patent extracts and removes the through-silicon interposer from the package structure, replacing it with a package substrate that has copper pillars directly connecting the chip to the circuit board. This eliminates the complex TSV manufacturing process while maintaining signal transmission functionality.
Solution Approach 2:
The patent replaces the expensive and complex through-silicon interposer with a simpler, more cost-effective package substrate structure using standard copper pillar technology, which is easier and cheaper to manufacture.
2Reliability
If through-silicon interposer with conductive elements is used, then electrical connection is achieved, but conductive performance and heat dissipation performance deteriorate
Solution Approach 1:
The patent changes the material parameters by replacing silicon-based conductive elements with copper pillars, which have superior electrical conductivity and thermal conductivity, thereby improving both conductive performance and heat dissipation.
Solution Approach 2:
The patent uses a composite structure combining the package substrate with copper pillars, leveraging the excellent electrical and thermal properties of copper to enhance overall performance.
3Reliability
If through-silicon interposer is disposed on package substrate via conductive elements, then electrical connection is achieved, but overall thickness cannot be reduced
Solution Approach 1:
The patent merges the functions of the through-silicon interposer and conductive elements into a single integrated package substrate structure with copper pillars, eliminating the need for separate components and reducing overall thickness.
Solution Approach 2:
The patent transitions from a multi-layer stacked structure (interposer + conductive elements + substrate) to a more compact integrated structure, effectively reducing the vertical dimension and overall package thickness.
4Reliability
If package substrate and through-silicon interposer are combined, then signal transmission is achieved, but thermal stress mismatch causes warpage and reliability problems
Solution Approach 1:
The patent changes the material composition by removing the silicon-based through-silicon interposer and using a package substrate with copper pillars, which have better thermal expansion compatibility, thereby reducing thermal stress mismatch and warpage.
5Reliability
If conventional manufacturing method with through-silicon interposer is used, then chip packaging is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates the expensive through-silicon interposer component and its associated complex manufacturing processes, replacing them with a more cost-effective package substrate structure.
Solution Approach 2:
The patent replaces the costly and complex TSV-based interposer with a simpler, cheaper package substrate using standard copper pillar technology, reducing manufacturing costs while maintaining functionality.
Data Source
AI summary
An electronic package is provided, in which one of insulating layers inside a package substrate is made of an Ajinomoto build-up film (ABF) material to facilitate the production of circuit structures using a redistribution layer (RDL) process, so that a circuit layer can meet the needs of high-density fine lines/fine spacing.