ABIST DFT Circuitry Verification Using LSSD Patterns
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Solution Overview
Problem
Current semiconductor test techniques using automatic test equipment do not adequately detect internal defects in VLSI devices, necessitating direct access to internal structures, which is addressed by Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and Built-In Self-Test (BIST) methods.
Innovation Solution
The method involves performing LSSD Flush and Scan tests followed by LSSD testing of DFT functional combinational logic using deterministic test patterns targeting ABIST design-for-test to ensure the microcode array's correct functioning, with additional tests terminated upon failure of ABIST DFT circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If automatic test equipment is used to apply test patterns at external inputs and measure responses at external outputs, then testing can be performed externally, but internal defects in VLSI devices cannot be adequately detected
Solution Approach 1:
The patent embeds test logic and storage elements directly within the VLSI device structure itself, nesting the testing capability inside the device being tested. This eliminates the need for complex external test equipment while enabling detection of internal defects through built-in test patterns and response capture mechanisms.
Solution Approach 2:
The VLSI device performs self-testing through built-in self-test (BIST) functionality, where the device generates its own test patterns, applies them to internal structures, and captures responses autonomously. This self-service approach eliminates dependency on external test equipment while achieving comprehensive internal defect detection.
2Reliability
If LSSD Flush and Scan tests are performed to determine scan chain operability, then scan chain functionality can be verified, but additional testing time is required before further testing can proceed
Solution Approach 1:
The patent performs LSSD Flush and Scan tests as preliminary actions before initiating further testing sequences. By verifying scan chain operability in advance, the system ensures that subsequent tests can proceed without interruption, and failed chips are identified early to avoid wasting time on futile testing operations.
Solution Approach 2:
Instead of performing exhaustive testing on all chips regardless of scan chain status, the patent inverts the approach by using the Flush and Scan test results to determine whether further testing should continue. This inversion eliminates unnecessary testing time for chips with failed scan chains while maintaining comprehensive testing for chips that pass the preliminary verification.
3Speed
If ABIST testing is performed on embedded arrays and memory elements, then at-speed testing can be achieved, but DFT supporting structures require additional verification to ensure correct functioning
Solution Approach 1:
The patent incorporates feedback mechanisms where LSSD test patterns are applied to DFT supporting structures (such as scan chains and multiplexers) that surround the ABIST arrays, and the responses are captured and analyzed. This feedback loop verifies the correct functioning of DFT structures, ensuring they properly support the high-speed ABIST operation without introducing undetected defects.
Solution Approach 2:
The patent segments the testing process into distinct phases: ABIST testing of embedded arrays for at-speed verification, and separate LSSD testing of DFT supporting structures for functional verification. This segmentation allows each component to be tested with appropriate methods, maintaining testing speed for arrays while ensuring DFT structure reliability through dedicated verification patterns.
Data Source
AI summary
A method, system and computer program product for testing the Design-For-Testability/Design-For-Diagnostics (DFT/DFD) and supporting BIST functions of a custom microcode array. Upon completion of the LSSD Flush and Scan tests, the ABIST program is applied to target the logic associated direct current (DC) and alternating current (AC) faults of ABIST array Design-For-Testability/Design-For-Diagnostics DFT/DFD functions that support the microcode array. A LSSD test of the DFT functional combinational logic is performed by applying generated LSSD deterministic test patterns targeting the ABIST design-for-test faults to determine if the DFT supporting the microcode array is functioning correctly. Additional tests may be terminated upon resulting failure of the applied ABIST DFT circuitry surrounding the arrays.