Abnormal Condition Detection Apparatus Using Signal Superposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional abnormal condition detection apparatuses for battery packs are inefficient in transmitting signals indicative of different types of abnormal conditions, requiring higher communication speeds and being cost-ineffective due to the need for multiple logic gates per abnormality type, and they can fail to transmit data within predetermined times at lower speeds.
Innovation Solution
The apparatus includes abnormal condition detection units on each battery block that transmit result signals driven low or high upon detection, with a logic gate at the branchpoint superimposing these signals onto a main line, reducing data transmission and eliminating the need for AND and OR circuits per abnormality type, using insulating interfaces to maintain consistent voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple logic gates (AND and OR circuits) are provided for each abnormality type to transmit different abnormal condition signals, then the reliability of abnormal condition detection is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges multiple logic gates (AND and OR circuits) into a single logic gate by encoding abnormal condition signals in a specific sequence. Instead of using separate logic gates for each abnormality type, the invention combines their functions into one gate that processes sequentially timed signals, thereby reducing device complexity while maintaining detection reliability
Solution Approach 2:
The single logic gate is designed to perform multiple functions by processing different types of abnormal condition signals through sequential timing. The gate handles both AND logic (for simultaneous conditions) and OR logic (for alternative conditions) functions using one universal component, eliminating the need for multiple specialized circuits
2Productivity
If data transmission speed is increased to transmit all abnormal condition data within predetermined time, then the productivity of data transmission is improved, but the manufacturing cost and system complexity increase
Solution Approach 1:
The patent applies periodic action by transmitting abnormal condition signals in sequential time periods rather than simultaneously. Each abnormality type is transmitted at a predetermined time interval, allowing the system to use lower communication speeds while still completing all data transmission within the required time frame
Solution Approach 2:
The system performs preliminary action by pre-establishing a transmission schedule where different abnormality types are assigned specific transmission times. This preliminary timing arrangement allows data to be transmitted efficiently without requiring high-speed communication infrastructure
3Reliability
If multiple logic gates per abnormality type are used to ensure reliable signal transmission, then the reliability is improved, but the manufacturing cost increases
Solution Approach 1:
The invention merges multiple logic gates into a single logic gate configuration, directly reducing the number of components that need to be manufactured and assembled. This consolidation maintains signal transmission reliability through sequential processing while lowering manufacturing costs by reducing part count and assembly complexity
Data Source
AI summary
A plurality of result signals are driven low when abnormal condition is detected and driven high when no abnormal condition is detected. Presence and absence of the abnormal conditions of different types are indicated in a predetermined sequence by high and low signal levels of the result signals. The voltage detecting circuits simultaneously output the result signals on corresponding branching lines connected to a main line of a communication line. An OR gate outputs a result signal on which the result signals output by the voltage detecting circuits are superimposed. When at least one of the result signals of the voltage detecting circuits is at a level indicative of the presence of the abnormal condition, the OR gate outputs on the main line the result signal having the level indicative of the abnormal condition.