Abnormality Detection Circuit Dynamic Key Verification
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Solution Overview
Problem
Existing watchdog timer circuits for CPU abnormality detection lack effective logical monitoring due to fixed or randomly changing key values, leading to insufficient monitoring of program sequences, especially when external bus masters interfere with the counter reset process.
Innovation Solution
An abnormality detection circuit that includes a counter, a seed value storage section, a calculator for generating a unique key value through specified arithmetic processing, and a comparator to ensure the counter is reset only when the generated key matches the written key, thereby maintaining logical monitoring and preventing external interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed key value is used for resetting the counter, then the device complexity is reduced, but the logical monitoring function becomes weak and cannot effectively monitor program sequence
Solution Approach 1:
The key value is transformed from a fixed static value to a dynamic value that changes with each counter reset operation. The calculator generates a new key value based on the current count value through arithmetic processing, making the key value adaptive to the program execution state and enabling effective logical monitoring.
Solution Approach 2:
The key value parameter is changed from a constant fixed value to a variable that is dynamically calculated. By using arithmetic processing on the count value to generate the key value, the system achieves both simplified device structure and enhanced monitoring capability.
2Reliability
If a read count value is used as key value, then randomness is obtained depending on program sequence operating status, but the monitoring function is insufficient and the key value can be changed by external bus masters
Solution Approach 1:
The calculator acts as an intermediary that processes the count value through arithmetic operations to generate the key value. This intermediary processing layer prevents direct access to the count value by external bus masters, thereby blocking interference while maintaining the randomness and monitoring capabilities.
Solution Approach 2:
The direct reading mechanism is replaced with an arithmetic processing mechanism. Instead of directly using the count value as the key, the system applies mathematical transformations (such as multiplication and addition) to generate the key value, which maintains security and monitoring function while preventing external interference.
3Reliability
If arithmetic processing is performed on seed value to generate key value, then logical monitoring capability is enhanced, but the device complexity increases due to additional calculator and comparator components
Solution Approach 1:
The calculator and comparator components serve multiple functions: generating key values, verifying key values, and enabling logical monitoring of program sequences. By making these components multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby mitigating the increase in device complexity.
Data Source
AI summary
An abnormality detection circuit and method of detecting an abnormality in a CPU is disclosed that may include counting a count value from an initial value to a timeout value; storing a seed value readable from the CPU; generating a key value for verification by performing a specified arithmetic processing on the seed value; waiting for a key value to be written by the CPU; comparing the key value written by the CPU with the key value for verification; and when the count value is equal to the timeout value without the counter being reset, in response to the key value and the key value for verification matching, resetting the counter and storing the seed value to be determined at the time of resetting the counter in the seed value storage section.