Abreast Chip Packaging Structure Reducing Thickness
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Solution Overview
Problem
Conventional multi-chip packages (MCPs) face challenges with increased thickness and bonding wire complexity due to vertical stacking, leading to larger size and vulnerability to stress-induced wire rupture.
Innovation Solution
A chip packaging structure where chips are arranged abreast with a transfer component, reducing the need for extensive bonding wires and substrate size, and utilizing a transfer component to facilitate electrical connections and reduce overall thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If chips are stacked vertically to integrate multiple chips, then the operating speed is improved, but the overall thickness increases
Solution Approach 1:
The patent transitions from vertical stacking (one-dimensional height increase) to horizontal arrangement (two-dimensional plane utilization). By arranging chips abreast on the substrate rather than stacking them vertically, the design achieves multi-chip integration while maintaining a reduced overall thickness profile.
2Quantity of substance
If the number of stacked chips increases, then the integration density is improved, but the number of bonding wires increases and wire bonding becomes difficult
Solution Approach 1:
The patent extracts and eliminates the need for extensive bonding wire networks by adopting direct chip-to-substrate bonding. By removing the vertical stacking configuration that requires multiple bonding wires between chips and substrate, the design simplifies the interconnection structure while maintaining multi-chip integration.
Solution Approach 2:
The substrate serves as an intermediary platform that directly bonds to multiple chips arranged abreast. This intermediary approach eliminates the need for complex bonding wire interconnections between stacked chips, as the substrate provides direct electrical and mechanical support to all chips in the array.
3Reliability
If bonding wires are used to connect chips with substrate, then electrical connection is achieved, but the wires are prone to rupture due to concentrated stress
Solution Approach 1:
The patent extracts and eliminates the vulnerable bonding wires from the system by implementing direct chip-to-substrate bonding. This removal of the wire interconnection layer eliminates the stress concentration points that lead to wire rupture, thereby improving the mechanical strength and reliability of the electrical connections.
4Reliability
If the substrate size is increased to accommodate multiple bonding wires, then the electrical connections are improved, but the overall width or length increases
Solution Approach 1:
The patent utilizes the two-dimensional plane of the substrate more efficiently by arranging chips in an abreast configuration. This allows multiple electrical connections to be established within a smaller substrate area by distributing chips across the surface rather than requiring a larger substrate to accommodate extended bonding wire routes.
Data Source
AI summary
A chip packaging structure and a manufacturing method for the same are provided. The chip packaging structure includes a first chip, a second chip and a transfer component. The first chip has a plurality of first bonding pads formed on the top surface of the first chip. The second chip has a plurality of second bonding pads formed on the top surface of the second chip. The first chip and the second chip are arranged abreast and electrically connected to each other. The transfer component is disposed on the top surface of the first chip and electrically connected with the first chip. Via these arrangements, the chip packaging structure can have smaller dimensions.