Absolute Difference Circuit Using Bit Inversion
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Solution Overview
Problem
Efficiently performing absolute difference operations in processing circuits is challenging, especially when supporting different data element sizes, as it often requires additional circuitry and resources, leading to increased power consumption and reduced performance.
Innovation Solution
The implementation of processing circuitry that includes an adding stage, an inverting stage, and control circuitry to generate control information based on data element size and status information, allowing for selective inversion of bits to convert intermediate values into absolute difference values without the need for a second addition, thereby reducing circuitry requirements and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional circuitry is used to perform absolute difference operations with different data element sizes, then the operation can be performed, but additional circuitry and resources are required, leading to increased power consumption and reduced performance
Solution Approach 1:
The circuitry is designed to dynamically adapt to different data element sizes (e.g., 8-bit, 16-bit, 32-bit) through configurable control signals that adjust the operation parameters. The control circuitry receives the current data element size as input and generates appropriate control information to configure the adding and inverting stages, allowing the same hardware to efficiently handle variable-sized operations without requiring separate dedicated circuits for each size.
2Use of energy by moving object
If conventional circuitry is used to perform absolute difference operations with different data element sizes, then the operation can be performed, but additional circuitry and resources are required, leading to increased power consumption
Solution Approach 1:
The processing circuitry is designed as a universal structure that can perform absolute difference operations on data elements of various sizes using the same adding and inverting stages. The control circuitry configures these stages based on the input data element size, eliminating the need for multiple dedicated circuits and reducing overall power consumption while maintaining full functionality across different data sizes.
3Productivity
If a second addition is performed to convert intermediate values into absolute difference values, then accurate results are obtained, but circuit area increases and performance decreases
Solution Approach 1:
Instead of performing a second addition to convert intermediate values into absolute difference values, the invention uses an inverting stage that selectively inverts selected bits of the intermediate value based on control information. This inversion approach achieves the same mathematical result (converting signed difference to absolute difference) but with simpler, faster, and more area-efficient circuitry compared to a full addition operation.
Data Source
AI summary
An apparatus comprises processing circuitry for performing an absolute difference operation for generating an absolute difference value in response to the first operand the second operand. The processing circuitry supports variable data element sizes for data elements of the first and second operands and the absolute difference value. Each data element of the absolute difference value represents an absolute difference between corresponding data elements of the first and second operands. The processing circuitry has an adding stage for performing at least one addition to generate at least one intermediate value and an inverting stage for inverting selected bits of each intermediate value. Control circuitry generates control information based on the current data element size and status information generated in the adding stage, to identify the selected bits to be inverted in the inverting stage to convert each intermediate value into a corresponding portion of the absolute difference value.