Auto-Biased Self-Timed ESD Clamp Using Intrinsic Capacitance
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Solution Overview
Problem
Existing electrostatic discharge (ESD) protection circuits in integrated circuits are inadequate as they require large RC timer circuits, leading to increased leakage currents, unintended triggering, and sensitivity to trailing electrical overstress, while also being inefficient in size and power consumption.
Innovation Solution
The auto-biased self-timed (ABST) ESD clamp uses RC-triggering only for initial turn-on and relies on the ESD event to generate bias voltage, operating at the transition between MOS-mode and bipolar-mode, with elevated substrate potential for self-sustaining conduction during the ESD pulse, eliminating the need for substrate pumping and silicide blocking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional RC timer circuits are used for ESD protection, then the device can provide ESD clamping function, but the leakage current increases and the device size increases
Solution Approach 1:
The patent extracts the timing function from the traditional RC timer circuit and implements it through the intrinsic capacitance of the PMOS transistor and a simplified resistor connection. This removes the need for large dedicated RC timer components, thereby reducing leakage current and device size while maintaining ESD protection capability.
Solution Approach 2:
The PMOS transistor serves multiple functions: it acts as the ESD clamp switch, provides timing functionality through its intrinsic capacitance, and generates bias voltage during ESD events. This multi-functionality eliminates the need for separate dedicated components, reducing overall device size and power consumption.
2Reliability
If traditional RC timer circuits are used for ESD protection, then the device can provide ESD clamping function, but the device complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex RC timer circuitry by using the intrinsic capacitance of the PMOS transistor and a simplified resistor connection. This dramatically reduces circuit complexity while maintaining the essential timing and protection functions.
Solution Approach 2:
The patent merges the ESD clamp switch, timing function, and bias generation into a single integrated structure using the PMOS transistor and minimal external components. This consolidation simplifies the overall circuit architecture and reduces the number of discrete components required.
3Productivity
If transistor size is reduced to increase integration density, then more transistors can be arranged, but the voltage withstand capability decreases making devices more susceptible to ESD damage
Solution Approach 1:
The patent changes the operational parameters of the PMOS transistor by utilizing its intrinsic capacitance and threshold voltage characteristics to provide timing and protection functions. This allows small transistors to achieve ESD protection capability through clever circuit design rather than relying on large physical dimensions.
Solution Approach 2:
The PMOS transistor uses its own intrinsic capacitance and electrical characteristics to provide timing and protection functions, eliminating the need for larger external components. This self-service approach enables ESD protection in compact transistor designs, maintaining both high integration density and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ABST clamp provides robust ESD protection with reduced leakage, immunity to false triggering, and smaller size, independent of RC time constant, and lower power consumption, effectively addressing the limitations of prior art.
Implementation Method 1
an RC trigger circuit, the RC trigger circuit comprising the capacitor and the resistor
Implementation Method 2
a first input of an OR logic block coupled to a first plate of the capacitor, a second input of the OR logic block coupled to a second plate of the capacitor
Implementation Method 3
a first transistor, the first transistor comprising a first source/drain and a second source/drain
Data Source
AI summary
Electrostatic discharge clamp devices are described. In one embodiment, the semiconductor device includes a first transistor, the first transistor including a first source/drain and a second source/drain, the first source/drain coupled to a first potential node, the second source/drain coupled to a second potential node. The device further includes a OR logic block, a first input of the OR logic block coupled to the first potential node through a capacitor, the first input of the OR logic block being coupled to the second potential node through a resistor, and a second input of the OR logic block coupled to a substrate pickup node of the first transistor.