Abstract Machine Livelock Checking for Hardware Verification
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Solution Overview
Problem
Current methods for livelock/deadlock checking in hardware verification are impractical due to the large size and complexity of real designs, making it difficult to check the entire design effectively.
Innovation Solution
The system constructs an abstract machine by identifying a finite state machine (FSM) and a subset of state variables within its cone of influence, searching for livelocks, and verifying their presence in the concrete machine through trace concretization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If livelock checking is performed on the whole design, then checking accuracy is improved, but computational complexity increases
Solution Approach 1:
The patent divides the entire design into multiple cones of influence (COI), each associated with a specific finite state machine (FSM). Instead of analyzing the whole design at once, the system segments the verification task into smaller, manageable COI portions. This allows livelock checking to be performed on individual COI segments independently, reducing computational complexity while maintaining accuracy for each segment.
Solution Approach 2:
The patent extracts only the relevant state variables and sequential elements that form each cone of influence, separating them from the rest of the design. By taking out only the necessary components (FSM and its COI) for analysis, the system reduces the verification scope to manageable subsets while preserving the integrity of livelock detection within those subsets.
2Ease of manufacture
If conventional techniques are used for livelock checking, then implementation simplicity is improved, but scalability worsens
Solution Approach 1:
The patent applies segmentation by dividing the design into multiple cones of influence, each verifiable independently using standard formal verification tools. This segmentation enables the system to scale to large designs with hundreds of thousands of sequential elements by processing multiple small COI segments rather than one large entire design, thus improving scalability while maintaining implementation simplicity through use of existing tools.
Solution Approach 2:
The patent performs partial action by verifying only the relevant cone of influence for each FSM rather than the entire design. This partial verification approach is sufficient to detect livelocks affecting specific FSMs without requiring exhaustive analysis of all design elements, thereby improving scalability while keeping the implementation approach simple and manageable.
3Reliability
If the entire cone of influence is analyzed, then livelock detection completeness is improved, but verification time increases
Solution Approach 1:
The patent segments the verification task into multiple independent cone of influence analyses, each completed in parallel or sequential order. By dividing the total verification work into smaller COI segments, the system achieves complete livelock detection across the entire design while reducing the time required for each individual analysis pass, allowing for more efficient resource utilization and faster overall verification.
Data Source
AI summary
Some embodiments of the present invention provide systems and techniques for checking a livelock in a circuit design. During operation, the system can identify a finite state machine (FSM) in the circuit design, wherein the FSM comprises a first set of state variables. The system can then construct an abstract machine of the circuit design, wherein the abstract machine includes the FSM and a second set of state variables. Next, the system can search for one or more livelocks in the abstract machine. If a livelock is found in the abstract machine, the system can verify that the livelock is a livelock in a concrete machine of the circuit design, wherein the concrete machine includes the FSM and a third set of state variables, wherein the second set of state variables is a subset of the third set of state variables.


