Abstract Memory Addressing via Pointer Registers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing memory addressing systems, which rely on Memory Management Units (MMUs) in the critical timing path, cause delays in memory access due to the need for physical address handling by the processor.
Innovation Solution
The system generates relative memory addresses that are added to base addresses stored in registers to produce physical addresses, eliminating the need for a MMU in the critical timing path, allowing multiple processes to access different sections of memory without delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Memory Management Unit (MMU) is used to map addresses and detect out of range memory accesses, then memory management functionality is provided, but memory access delay is caused due to the MMU being in the critical timing path
Solution Approach 1:
The patent extracts the MMU functionality from the critical timing path by using pointer registers to store physical addresses. The processor only needs to generate relative addresses and add them to base addresses stored in registers, eliminating the need for MMU intervention during critical memory access operations. This separation removes the timing constraint imposed by the MMU while preserving memory management capabilities through register-based address translation.
Solution Approach 2:
The patent performs address translation in advance by pre-loading base addresses into pointer registers. The physical addresses are prepared before the critical memory access operation, allowing the processor to directly access memory using simple addition of relative addresses to pre-computed base addresses. This preliminary action eliminates the need for real-time MMU translation during the critical timing path.
2Reliability
If physical addresses are handled by the processor through an MMU, then memory access control is achieved, but processor workload increases
Solution Approach 1:
The patent extracts complex address translation and validation logic from the processor by implementing it through dedicated pointer registers. The processor's role is simplified to generating relative addresses and performing basic addition operations, while the pointer registers handle the cumbersome tasks of physical address storage, retrieval, and validation. This extraction significantly reduces processor workload while maintaining robust memory access control.
Solution Approach 2:
The pointer registers perform self-service by automatically handling address translation and validation without requiring processor intervention. The registers maintain their own state with base addresses and enable the processor to access memory through simple relative address addition, eliminating the need for the processor to manually manage complex address mapping and validation operations.
3Adaptability or versatility
If multiple base registers are used to support different processes accessing different memory sections, then system versatility is improved, but device complexity increases
Solution Approach 1:
The patent segments the memory address space into separate sections, each associated with a dedicated pointer register. Each process or memory section has its own base address stored in a separate register, allowing independent management of different memory regions. This segmentation enables multiple processes to access different memory sections simultaneously without interference, achieving high versatility through a systematic division of address management responsibilities.
Data Source
AI summary
An apparatus for abstract memory addressing. A processor for generating an abstract memory address. A base register for storing a base memory address. An adder for adding the base memory address to the abstract memory address and generating a physical address for a device memory. A pointer register for storing the physical address, wherein the pointer register is directly coupled to the device memory.