Abutted Integrated Circuit Blocks Using Finishing Cells
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Solution Overview
Problem
In integrated circuits, independently designed blocks often occupy inefficient space due to the need for halo regions between them, limiting the overall layout area and increasing complexity as device sizes decrease.
Innovation Solution
The method involves placing blocks such that their finishing cells abut each other, eliminating the need for halo regions by using transition cells or dummy regions, allowing for more optimal placement and reduced layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If halo regions are placed between independently designed blocks, then manufacturing reliability is improved, but layout area increases and design efficiency deteriorates
Solution Approach 1:
The patent extracts the halo region requirement from the block placement design by introducing finishing cells that inherently provide the necessary halo functionality. Instead of placing separate halo regions between blocks, the finishing cells are designed to extend along block boundaries and abut adjacent blocks, thereby eliminating the need for additional halo spaces while maintaining manufacturing reliability.
Solution Approach 2:
The finishing cells serve multiple functions: they terminate function cell arrays at block boundaries, provide halo regions for manufacturing reliability, and enable abutment between adjacent blocks. This multi-functionality resolves the contradiction by combining the halo region provision with the block boundary definition, eliminating the need for separate halo regions.
2Reliability
If blocks are placed with halo regions between them, then manufacturing reliability is improved, but device integration density deteriorates
Solution Approach 1:
The patent removes the separate halo region requirement by integrating halo functionality into the finishing cells. The finishing cells extend along block boundaries and abut adjacent blocks, extracting the halo function from a separate structural element and incorporating it into the block design itself, thereby increasing integration density while maintaining reliability.
Solution Approach 2:
The patent merges the halo region provision with the finishing cell structure. Instead of having separate halo regions between blocks, the finishing cells are designed to provide both block boundary definition and halo functionality simultaneously, merging two previously separate requirements into a single integrated solution that improves device integration density.
3Productivity
If finishing cells extend along block boundaries, then layout optimization is improved, but block complexity increases
Solution Approach 1:
The patent segments the block structure into function cell arrays and finishing cells, with finishing cells specifically positioned at block boundaries. This segmentation allows the finishing cells to handle boundary-specific requirements (halo regions, abutment) while the interior function cell arrays maintain their original simplicity, thereby optimizing layout without excessively increasing overall block complexity.
Solution Approach 2:
The patent applies local quality by giving finishing cells at block boundaries special properties (extending to provide halo and abutment functionality) while leaving interior function cells with standard properties. This localized enhancement of boundary cells achieves layout optimization without requiring complex modifications throughout the entire block structure.
Data Source
AI summary
Integrated circuits including abutted blocks and methods of designing layouts of the integrated circuits are disclosed. The integrated circuit includes a first block having a first function cell array therein, which is at least partially surrounded by a first plurality of finishing cells, and a second block extending adjacent the first block. The second block includes a second function cell array therein, which is at least partially surrounded by a second plurality of finishing cells. The first plurality of finishing cells include: (i) a first finishing cell placed at a boundary of the integrated circuit, and (ii) a second finishing cell different from the first finishing cell, which is placed at a boundary between the first block and the second block.