AC Differential Amplifier Feedback Topology for Low Corner Frequency
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Solution Overview
Problem
Existing AC amplifiers face challenges in achieving a low corner frequency with reduced parasitic capacitance and current consumption, especially in integrated circuits, where large decoupling capacitors increase input capacitance and noise, and require expensive fabrication techniques.
Innovation Solution
A differential AC amplifier architecture is developed with a degeneration network that includes a capacitive network and a second differential pair of transistors, connected in series to the current nodes of the first differential pair, which forms a high-frequency feedback loop, allowing the low corner frequency to be determined by the capacitive network and transistor resistance, rather than parasitic capacitances, while maintaining unchanged input capacitance and bias current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If large decoupling capacitors are used to achieve low corner frequency, then the low corner frequency is reduced, but parasitic capacitances and input capacitance increase significantly
Solution Approach 1:
The decoupling function is segmented from the input capacitance path. The first decoupling capacitor is placed at the input of the differential pair, while the second decoupling capacitor is placed at the output of the differential pair, separating the DC decoupling function from the signal path to minimize parasitic capacitance impact on input capacitance.
Solution Approach 2:
The differential pair acts as an intermediary between the input signal and the decoupling capacitors. By placing decoupling capacitors at both inputs and outputs of the differential pair, the parasitic capacitances are isolated from the direct input path, effectively reducing their impact on input capacitance while maintaining low corner frequency performance.
2Speed
If large decoupling capacitors are used to achieve low corner frequency, then the low corner frequency is reduced, but noise increases
Solution Approach 1:
The noise contribution is segmented by placing decoupling capacitors at both inputs and outputs of the differential pair. This segmentation allows the large capacitance values needed for low corner frequency to be distributed, reducing the noise impact on the input signal while maintaining the desired frequency response.
Solution Approach 2:
The differential pair and its associated decoupling capacitors act as intermediaries that isolate the noise generated by large capacitors from the input signal path. The dual decoupling configuration ensures that noise from large capacitors does not directly couple to the input, maintaining low noise performance while achieving low corner frequency.
3Object-affected harmful factors
If decoupling capacitors are placed to reduce parasitic capacitance impact, then input capacitance is maintained, but current consumption increases
Solution Approach 1:
The decoupling function is merged with the differential pair structure by placing decoupling capacitors at both inputs and outputs. This merging allows the circuit to achieve low input capacitance while maintaining low corner frequency without requiring additional active components that would increase current consumption, as the same differential pair handles both signal amplification and decoupling functions.
Data Source
AI summary
An integrated amplifier may include a transconductance stage including a differential pair of input transistors of a first type of conductivity, respective resistive loads coupled to said input transistors, and a first bias circuit coupled to the input transistors. The first bias circuit may include a second differential pair of bias transistors having first conduction terminals coupled in common and second conduction terminals coupled to respective conduction terminals of the input transistors. The first bias circuit may also include respective second bias circuits coupled to the bias transistors to enable the input transistors in a conduction state with the input transistors being biased by a same respective bias current that flows through the respective input transistors. The first bias circuit may also include a capacitive network coupled to the bias transistors to define with the input transistors a feedback loop.