AC Coupled Clock Receiver Common-Mode Noise Rejection
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Solution Overview
Problem
Communication systems with differential clock signals are susceptible to common-mode noise, leading to increased data errors and reduced manufacturing yields due to the complexity and power consumption of clock recovery circuits in receivers.
Innovation Solution
A clock receiver is designed with a capacitive coupling circuit for high-pass filtering, a bias circuit for introducing bias voltage, and a differential amplifier for amplifying and generating feedback signals to reject common-mode noise in differential clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock recovery circuit is used in the receiver to reconstruct the transmit clock signal, then the receiver can extract data from the data signal, but the circuit complexity increases and manufacturing yield decreases
Solution Approach 1:
The patent extracts the clock signal transmission function from the data signal transmission, using a separate differential clock signal path. This eliminates the need for complex clock recovery circuits while maintaining data extraction capability, as the receiver directly uses the transmitted differential clock signal for data sampling.
Solution Approach 2:
The differential clock signal serves multiple functions: it provides timing synchronization for data extraction and acts as a reference for common-mode noise rejection. By making the clock signal multi-functional, the patent eliminates the need for separate clock recovery circuitry while maintaining reliable data extraction.
2Reliability
If a clock recovery circuit is included in the receiver, then data can be extracted using the reconstructed clock signal, but the area and power consumption increase
Solution Approach 1:
The patent removes the power-consuming clock recovery circuitry by extracting the clock function from data signal processing. The receiver directly uses the transmitted differential clock signal, eliminating the need for power-intensive phase-locked loops and clock reconstruction circuits.
3Device complexity
If differential clock signal is used to reduce circuit complexity, then manufacturing yield improves, but common-mode noise causes jitter in the single-ended clock signal
Solution Approach 1:
The patent employs a feedback mechanism where the differential clock signal is used to generate a reference signal that is fed back to the data reception circuit. This feedback loop enables common-mode noise rejection by comparing the differential clock phases and canceling out noise components, thereby reducing jitter in the effective clock signal.
Solution Approach 2:
The patent uses a composite signaling approach combining differential voltage signaling with phase-comparison-based noise rejection. By composite the differential clock signal with feedback-based common-mode rejection processing, the system maintains simplicity while eliminating noise susceptibility.
4Productivity
If the frequency of the differential clock signal is increased to improve data transmission rate, then productivity increases, but jitter increases and data error rate increases
Solution Approach 1:
The feedback mechanism using the differential clock signal provides real-time phase comparison and jitter compensation. As clock frequency increases, the feedback loop actively compensates for increased jitter by dynamically adjusting the sampling timing, thereby maintaining low error rates even at high data transmission rates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces common-mode noise in differential clock signals, improving data accuracy and reducing power consumption and complexity in integrated circuit receivers.
Implementation Method 1
a capacitive coupling circuit for filtering out direct-current voltages from a differential clock signal. In this way, the capacitive coupling circuit rejects common-mode noise in the differential clock signal
Implementation Method 2
a differential amplifier for amplifying the differential clock signal. Further, the differential amplifier generates a feedback differential clock signal and provides the feedback differential clock signal to the bias circuit for further rejecting common-mode noise in the differential clock signal
Data Source
AI summary
A clock receiver includes a capacitive coupling circuit for filtering out direct-current voltages from a differential clock signal. In this way, the capacitive coupling circuit rejects common-mode noise in the differential clock signal. The clock receiver also includes a bias circuit for establishing a bias voltage in the differential clock signal and a differential amplifier for amplifying the differential clock signal. Further, the differential amplifier generate a feedback differential clock signal and provides the feedback differential clock signal to the bias circuit for further rejecting common-mode noise in the differential clock signal. The feedback differential clock signal functions as a negative feedback signal for rejecting common-mode noise in the differential clock signal and as a positive feedback signal for amplifying the differential clock signal. In some embodiments, the clock receiver includes a capacitive coupling circuit with a cut-off frequency above the frequency of the differential clock signal.