AC-Coupled Bias Ladder FET Stacks for High-Voltage RF Switching
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Solution Overview
Problem
Existing RF switch circuits using FET stacks face challenges in handling high voltage RF signals without requiring a negative bias voltage, as they often suffer from high insertion loss, mismatch loss, and are prone to breakdown due to the limitations of positive logic FET stacks.
Innovation Solution
The implementation of a positive-logic FET switch stack that does not require a negative bias voltage, utilizing series-connected bias resistor ladders and end-cap FETs that provide either capacitive DC blocking or resistive signal paths, along with optional end-cap capacitors to prevent early breakdown, and AC coupling modules for improved voltage handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If positive logic FET stacks are used to avoid negative bias voltage, then device complexity is reduced, but voltage handling capability deteriorates leading to breakdown
Solution Approach 1:
The FET stack is divided into multiple segments with different gate voltages applied to different portions. The first portion operates at a first gate voltage while the second portion operates at a second gate voltage, allowing each segment to handle a portion of the total voltage stress and preventing breakdown of the entire stack.
Solution Approach 2:
Different gate voltages are applied to different portions of the FET stack based on their specific voltage handling requirements. The first portion receives a first gate voltage optimized for its operating conditions, while the second portion receives a second gate voltage optimized for its conditions, allowing each local region to operate at optimal performance without compromising overall reliability.
2Reliability
If series-connected FET stacks are used to increase voltage handling, then voltage handling capability is improved, but insertion loss increases
Solution Approach 1:
The series-connected FET stack is segmented into portions with different gate voltages, allowing optimization of each segment's contribution to insertion loss while maintaining the total voltage handling capability. This reduces the cumulative insertion loss compared to a uniform series stack.
Solution Approach 2:
By changing the gate voltage parameter across different portions of the stack, the invention optimizes the trade-off between voltage handling and insertion loss. Different gate voltages alter the channel characteristics of each FET portion, reducing overall signal attenuation while maintaining voltage blocking capability.
3Reliability
If more FETs are stacked in series to handle higher voltages, then voltage handling capability is improved, but device area increases
Solution Approach 1:
The FET stack is segmented into portions that can be arranged in a compact configuration on the IC. By dividing the stack and applying different gate voltages to different portions, the design achieves high voltage handling in a reduced area compared to a single long series stack.
Solution Approach 2:
The invention utilizes vertical stacking of FETs in the third dimension rather than spreading them out in the planar IC area. Multiple FETs are stacked vertically to handle high voltages while maintaining a compact footprint, effectively transitioning from two-dimensional layout to three-dimensional structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high isolation, low insertion loss, and reduced IC area usage while enabling the switch stack to withstand high voltage RF signals, with improved switching speed and reduced power consumption.
Implementation Method 1
The AC coupling module may comprise a capacitor
Implementation Method 2
The end-cap FETs may be configured to provide a capacitive DC blocking function
Data Source
AI summary
A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.