AC-Coupled Source Follower With Self-Biased MOS Load for Stable Bias
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Solution Overview
Problem
Existing source follower circuits with local negative feedback loops face instability in DC bias and are not suitable for high-linearity applications in modern CMOS processes, particularly when used in low-power receivers with low supply voltages.
Innovation Solution
A source follower circuit design incorporating self-biased diode-connected MOS loads and AC-coupled feedback paths to stabilize DC bias and enhance linearity, using reference current generators to adjust drain voltage levels and increase output voltage swing range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a local negative feedback loop with direct current coupling path is adopted, then the output impedance can be lowered further, but it is not suitable for high-linearity application with modern advanced CMOS process
Solution Approach 1:
The patent introduces an AC coupling capacitor as an intermediary element between the feedback path and the output node. This capacitor blocks DC components while allowing AC signals to pass through, enabling the feedback loop to improve linearity without directly coupling DC paths that are incompatible with modern CMOS processes. The capacitor acts as a mediator that separates the AC signal feedback function from the DC biasing requirements.
2Adaptability or versatility
If a local feedback path formed with a floating capacitor is adopted, then bias flexibility can be improved, but the DC bias of an internal node becomes unstable
Solution Approach 1:
The patent segments the feedback path into separate AC and DC components using the coupling capacitor. The AC feedback path through the capacitor provides bias flexibility for signal processing, while the DC biasing is handled separately through dedicated biasing circuits and resistive dividers. This segmentation allows independent optimization of AC performance and DC stability without mutual interference.
Solution Approach 2:
The coupling capacitor serves as an intermediary that decouples the AC feedback signal from the DC bias network. This allows the DC bias of internal nodes to be stabilized through separate biasing mechanisms while the AC feedback path maintains flexibility for different bias conditions. The capacitor mediates between the conflicting requirements of bias flexibility and DC stability.
3Use of energy by moving object
If the circuit is designed for low-power operation with low supply voltages, then power consumption is reduced, but the output voltage swing range is limited
Solution Approach 1:
The patent employs dynamic biasing techniques where the bias points of the circuit are optimized for different operating conditions. The feedback loop dynamically adjusts the operating point to maximize output swing within the constrained supply voltage range. This dynamic adaptation allows the circuit to maintain low power consumption while extracting maximum possible voltage swing from the limited supply rails.
Solution Approach 2:
The patent changes key circuit parameters such as transistor sizing, feedback factor, and bias currents to optimize the trade-off between power consumption and output swing. By carefully selecting and adjusting these parameters, the circuit achieves efficient operation at low supply voltages while maintaining adequate output voltage swing range for practical applications.
Data Source
AI summary
A source follower circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, and a feedback loop circuit. Regarding the first MOS transistor, a gate terminal receives an input signal of the source follower circuit, and a source terminal outputs an output signal of the source follower circuit. Regarding the second MOS transistor, a gate terminal is coupled to a bias voltage, a source terminal is coupled to a first reference voltage, and a drain terminal is coupled to the source terminal of the first MOS transistor. Regarding the third MOS transistor, it is a self-biased diode-connected MOS transistor with its gate terminal coupled to its drain terminal. The drain terminal of the third MOS transistor is coupled to a drain terminal of the first MOS transistor, and a source terminal of the third MOS transistor is coupled to a second reference voltage.