AC Noise Reduction in 3D Chip Stacks via Voltage Sensing and Clock Shifting
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Solution Overview
Problem
In 3D stacked chips, simultaneous clock switching generates significant alternating current (AC) supply noise due to the power and ground power grids, which existing technologies have not effectively addressed.
Innovation Solution
The implementation of voltage droop sensors and skew adjusters on each stratum of the 3D chip stack to detect AC supply noise and delay clock signals, thereby reducing noise by shifting peak power draw across different strata.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simultaneous clock switching is used in synchronous clock systems, then clock synchronization is achieved, but AC supply noise increases significantly
Solution Approach 1:
The patent divides the simultaneous clock switching operation into sequential operations across different strata. Each stratum switches its clock signals at different times rather than simultaneously, segmenting the noise-generating event into multiple smaller, time-separated events. This reduces peak AC supply noise while maintaining overall clock synchronization functionality.
Solution Approach 2:
The patent implements periodic clock switching where each stratum enables its clock signals in alternating time periods. Stratum 0 switches clocks during one time period while stratum 1 switches during another time period, creating a periodic pattern that distributes noise over time rather than concentrating it at one moment, thereby reducing peak AC supply noise.
2Object-generated harmful factors
If clock signals are delayed to reduce noise, then AC supply noise is reduced, but clock skew increases
Solution Approach 1:
The patent employs dynamic skew adjustment where the delay applied to clock signals is not fixed but can be adjusted based on operating conditions. The system dynamically balances the noise reduction benefit against the clock skew penalty, optimizing the delay amount to achieve acceptable noise reduction while maintaining timing synchronization within tolerance limits.
Solution Approach 2:
The patent changes the timing parameter of clock signals by introducing controllable delays to different strata. By adjusting the clock enable time parameter for each stratum, the system modifies when clocks switch states, thereby controlling the noise profile while managing the resulting clock skew through parameter optimization.
Data Source
AI summary
There is provided an alternating current supply noise reducer for a 3D chip stack having two or more strata. Each of the strata has a respective one of a plurality of power distribution circuits and a respective one of a plurality of clock distribution circuits arranged thereon. The alternating current supply noise reducer includes a plurality of voltage droop sensors and a plurality of skew adjustors. The plurality of voltage droop sensors is for detecting alternating current supply noise in the plurality of power distribution circuits. One or more voltage droop sensors are respectively arranged on at least some of the strata. The plurality of skew adjusters are for delaying one or more clock signals provided by the plurality of clock distribution circuits responsive to an amount of the alternating current supply noise. Each skew adjuster is respectively arranged on the at least some of the strata.