AC Vehicle Controller FPGA Parallel Arithmetic Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional AC electric vehicle controllers using DSP for software arithmetic processing face limitations in processing speed, leading to reduced control accuracy and interference with return harmonics due to asynchronous data exchange between hardware and software modules.
Innovation Solution
The controller divides arithmetic processing into parallel blocks configured by an FPGA, enabling simultaneous processing to maintain high-speed operations and reduce harmonic impacts, while allowing software adjustments for gain and filter constants to simplify setup.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If arithmetic processing is performed by software using DSP, then control accuracy can be maintained through floating-point operations, but processing speed is limited and asynchronous timing delays occur
Solution Approach 1:
The arithmetic processing is divided into multiple independent processing blocks (first arithmetic processing block, second arithmetic processing block, third arithmetic processing block) that can operate simultaneously. Each block handles specific arithmetic operations (addition, subtraction, multiplication, division) independently, enabling parallel execution while maintaining precision through fixed-point arithmetic designed to match floating-point accuracy.
Solution Approach 2:
The patent replaces the software-based DSP arithmetic processing with hardware-based FPGA arithmetic processing. This substitution transitions from sequential software execution to parallel hardware execution, dramatically improving processing speed while eliminating asynchronous timing delays between hardware and software modules.
2Speed
If arithmetic processing is performed by FPGA with fixed-point operations, then processing speed increases, but more bits are required to achieve the same arithmetic accuracy
Solution Approach 1:
The patent changes the arithmetic parameter representation from floating-point (software) to fixed-point (hardware), and specifically designs the fixed-point arithmetic with optimized bit allocations. The first arithmetic processing block uses 16-bit operands with 8-bit results, the second block uses 16-bit operands with 16-bit results, and the third block uses 32-bit operands with 32-bit results, ensuring adequate precision for each operation type while maintaining high processing speed.
3Device complexity
If sequential arithmetic operations are performed, then device complexity is reduced, but processing time increases and control accuracy deteriorates
Solution Approach 1:
The controller structure is segmented into three independent arithmetic processing blocks that can execute simultaneously. Each block is relatively simple in design, handling specific arithmetic operations, but their parallel execution dramatically reduces total processing time without significantly increasing overall device complexity.
Solution Approach 2:
The patent transitions from sequential (one-dimensional) arithmetic processing to parallel (multi-dimensional) processing by executing multiple arithmetic operations simultaneously in different processing blocks. This dimensional change in processing architecture reduces processing time while keeping individual block complexity manageable.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
In a controller for an AC electric vehicle that includes a converter control unit 20 controlling an operation of a PWM converter 3 that converts an AC voltage inputted from an AC overhead line through a transformer into an DC voltage, arithmetic processing performed in the converter control unit 20 is divided into at least first to sixth arithmetic processing blocks, the first to sixth arithmetic processing blocks are configured by an FPGA, and the first to third arithmetic processing blocks, and the fourth and fifth arithmetic processing blocks are configured to enable simultaneous parallel processing, respectively.