AC Voltage Monitoring Circuit with Zero-Crossing Timed Thresholding
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Solution Overview
Problem
Existing circuit arrangements for monitoring sinusoidal alternating voltage signals, particularly in devices like programmable logic controllers, face challenges in using comparators due to the difference between peak and effective voltage values, leading to reduced threshold ranges and inefficiency when monitoring both AC and DC signals.
Innovation Solution
A circuit arrangement that includes a comparator, zero-crossing detector, and timing element, allowing for flexible threshold settings by shifting the evaluation time relative to the zero crossing of the sinusoidal signal, enabling the use of comparators with tolerances and allowing monitoring of both AC and DC signals with a single threshold value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a comparator with a fixed threshold value is used to monitor AC input signals, then the monitoring can be performed with simple components, but the threshold range is reduced and reliable operation cannot be ensured due to the difference between peak and RMS values
Solution Approach 1:
The patent changes the temporal parameter of signal evaluation by introducing a delayed sampling approach. Instead of evaluating the AC signal at its peak value, the system evaluates it at a delayed time point after the zero crossing, effectively changing when the measurement is taken. This allows the use of a fixed threshold value in the comparator while still achieving reliable RMS-based monitoring, as the delayed evaluation point corresponds to a specific relationship between peak and RMS values.
Solution Approach 2:
The patent performs preliminary action by detecting the zero crossing point of the AC signal and calculating a predetermined delay time before the peak occurrence. This preliminary timing information is stored and used to trigger the comparator at the optimal moment. By preparing the timing information in advance, the system ensures that the comparator evaluates the signal at the correct phase, maintaining reliability while using simple fixed-threshold components.
2Adaptability or versatility
If the evaluation time is shifted away from the peak value occurrence, then comparators with tolerances can be used, but the direct correlation between input signal and threshold comparison is modified
Solution Approach 1:
The patent introduces an intermediary element - a delay timer - that mediates between the zero crossing detection and the comparator evaluation. This timer calculates and enforces a predetermined delay time that corresponds to the difference between zero crossing and peak occurrence. The intermediary translates the timing relationship into a controlled evaluation moment, allowing the use of tolerance-prone comparators while maintaining the mathematical relationship between RMS and peak values through the fixed delay.
3Device complexity
If a single threshold value is used for both AC and DC signal monitoring, then device complexity is reduced, but the threshold must be optimized for AC peak values which reduces effectiveness for DC signals
Solution Approach 1:
The patent achieves universality by making the evaluation timing adaptable to different signal types. The system uses zero crossing detection specifically for AC signals to establish a timing reference, while DC signals can be monitored continuously without requiring zero crossing events. The predetermined delay time serves both AC and DC monitoring needs, allowing a single fixed threshold to work reliably for both signal types. The timing mechanism becomes universal, triggering appropriately whether AC zero crossings or DC signal conditions are detected.
Data Source
Figure 1A~1B
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AI summary
The invention relates to a circuit assembly for monitoring a sinusoidal alternating voltage signal (l_k) having a comparator (8), to which a sinusoidal alternating voltage signal (l_k) to be monitored or a signal obtained therefrom may be supplied at an input, wherein the comparator (8) is configured to generate a first output signal (Sl) at an output if the sinusoidal alternating voltage signal (l_k) or the signal obtained therefrom exceeds a specified threshold value (A). Further, a zero crossing detector (10) is provided, to which the sinusoidal alternating voltage signal (l_k) to be monitored or a signal obtained therefrom may be supplied at a monitoring input such that a second output signal (S2) may be generated at an output of the zero crossing detector (10). A timing element (12) is connected downstream of the zero crossing detector (10) to generate a clock signal (S3) dependent on the second output signal (S2). Furthermore, an edge controlled flip-flop (14) is provided, wherein the output from the comparator (8) is connected to an input (D) of the flip-flop (14), and wherein an output of the timing element (12) is connected to a clock input (Clk) of the flip-flop (14). The timing element (12) specifies a state change of the clock signal (S3) at a time that differs from a time at T/4 of a period T after a zero crossing of the sinusoidal alternating voltage signal (l_k).