Configurable Accelerated Post-Write Read for Flash Memory Error Management
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Solution Overview
Problem
Conventional error correction codes (ECC) in flash memory systems are resource-intensive and designed for worst-case error rates, leading to performance degradation and overhead, especially as the memory ages and error rates increase near the end of its life.
Innovation Solution
A method is introduced to partition the memory array into two portions, where data is initially written to a high-density portion with a smaller error margin and then checked for errors; if excessive errors are found, the data is rewritten to a lower-density portion with a wider error margin, allowing for a less complex ECC to be used, thereby improving performance and reducing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC is designed for worst-case error rates, then reliability is improved, but device complexity and resource usage increase
Solution Approach 1:
The patent changes the parameter of error rate assumption from worst-case to actual measured error rates. By monitoring actual error rates and adjusting ECC strength accordingly, the system achieves reliable error correction while avoiding the excessive complexity of worst-case ECC designs.
Solution Approach 2:
The patent implements dynamic adjustment of ECC parameters based on actual error rate measurements. The ECC strength is not fixed but adapts over time based on observed error patterns, allowing the system to optimize between reliability and complexity as conditions change.
2Quantity of substance
If high-density memory portion is used, then storage capacity is improved, but error rate increases
Solution Approach 1:
The patent applies different quality levels to different portions of the memory system. High-density memory is used where capacity is needed, while stronger error correction is applied locally to handle the higher error rates. This allows the system to maximize storage capacity while maintaining reliability through targeted error correction.
3Reliability
If post-write read is performed to check errors, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent implements error checking that serves the system's own reliability needs without requiring external intervention or significant performance penalty. By using sampled post-write reads and adaptive ECC, the system performs self-verification efficiently, maintaining high productivity while improving reliability.
4Quantity of substance
If memory is used near end of life, then existing capacity is maintained, but error rate increases
Solution Approach 1:
The patent implements continuous feedback monitoring of error rates in aging memory. As memory approaches end-of-life and error rates increase, the system receives feedback about deteriorating conditions and responds by adjusting ECC parameters or migrating data, allowing the system to maintain reliable operation throughout the memory's lifecycle.
Data Source
AI summary
Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. An error management provides reading and checking the copy after copying to the second portion. If the copy has excessive error bits, it is repeated in a different location either in the second or first portion. The reading and checking of the copy is accelerated by reading only a sample of it. The sample is selected from a subset of the copy having its own ECC, where the sample selected depends on the count of erase-program cycles that a block has experienced, where different count ranges can use different samples.