Hardware Accelerator Access Mode Control for Cache Pollution Prevention
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Solution Overview
Problem
Hardware accelerators in multi-user and multi-task operating systems face inefficiencies due to cache pollution and varying memory access patterns, as they often operate in non-temporal locality access mode, which can lead to suboptimal performance and cache pollution, while temporal locality access mode is not always utilized effectively.
Innovation Solution
A processing system that dynamically determines the access mode of a hardware accelerator based on instruction behavior, allowing it to switch between non-temporal and temporal access modes, thereby preventing cache pollution and improving access efficiency by directly accessing the host memory in non-temporal mode and the cache in temporal mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the hardware accelerator operates in non-temporal access mode, then the access speed for non-repeated data is improved, but cache pollution occurs
Solution Approach 1:
The hardware accelerator dynamically switches between non-temporal access mode and temporal access mode based on the access behavior characteristics of instructions. The controller determines whether to use non-temporal access or temporal access by analyzing instruction patterns, enabling the system to adaptively optimize performance while preventing cache pollution when non-temporal access is appropriate
2Productivity
If the hardware accelerator operates in temporal access mode, then the cache utilization is improved, but the access efficiency for non-temporal data deteriorates
Solution Approach 1:
The system dynamically adjusts the access mode based on instruction characteristics. When instructions exhibit temporal locality patterns, the hardware accelerator switches to temporal access mode to utilize cache effectively. When instructions show non-temporal access patterns, it switches to non-temporal mode to maintain high access efficiency, thus optimizing both cache utilization and access speed under different workloads
3Adaptability or versatility
If the hardware accelerator shares the cache with multiple CPU cores, then the resource utilization is improved, but the cache pollution from non-temporal access increases
Solution Approach 1:
In a multi-core CPU shared cache environment, the hardware accelerator controller analyzes instruction access behaviors to dynamically determine the appropriate access mode. By switching between temporal and non-temporal access modes based on actual instruction patterns, the system maximizes shared cache resource utilization while preventing cache pollution that would occur with unconditional non-temporal access
Solution Approach 2:
The controller monitors instruction access behaviors and uses this feedback to dynamically adjust the access mode. By analyzing whether instructions exhibit temporal or non-temporal locality patterns, the system makes informed decisions about cache access strategies, thereby optimizing resource utilization while minimizing harmful cache pollution effects
Data Source
AI summary
A processing system includes a cache, a host memory, a CPU and a hardware accelerator. The CPU accesses the cache and the host memory and generates at least one instruction. The hardware accelerator operates in a non-temporal access mode or a temporal access mode according to the access behavior of the instruction. The hardware accelerator accesses the host memory through an accelerator interface when the hardware accelerator operates in the non-temporal access mode, and accesses the cache through the accelerator interface when the hardware accelerator operates in the temporal access mode.