Accelerator Bit-Stream Preconfiguration for Low-Latency Job Execution

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Solution Overview

Problem

The existing accelerator devices face delays and performance reductions due to the time-consuming process of fetching and registering bit-streams, which hinders the acceleration of jobs and reduces the benefits of using these devices in applications like machine learning and genomics.

Innovation Solution

An orchestrator server predicts upcoming jobs and pre-configures accelerators by registering predicted bit-streams, reducing the time required for bit-stream registration and fetching, thereby enhancing the efficiency of accelerator utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the accelerator device fetches and registers bit-streams upon receiving a job request, then the accelerator can execute the requested job, but the fetching and registering process consumes non-trivial time, delaying job acceleration and reducing performance benefits

Engineering Contradiction:
Improvebit-stream registration timeVSAvoidjob acceleration efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The system predicts upcoming jobs and pre-registers their corresponding bit-streams on accelerators before the jobs are actually submitted. This preliminary action eliminates the registration delay that would otherwise occur when jobs are received, as the bit-streams are already prepared and ready for immediate execution.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system monitors job submission patterns and accelerator utilization to dynamically adjust prediction accuracy and optimize pre-registration strategies. By incorporating feedback from actual job workloads, the system refines its predictions and improves the timing of bit-stream pre-registration to minimize delays while avoiding unnecessary pre-processing.

Inventive Principle:
Principle #23Feedback

2Productivity

If the accelerator device waits for job requests to fetch and register bit-streams, then resource utilization is optimized, but the latency associated with traditional bit-stream registration processes reduces overall system efficiency

Engineering Contradiction:
Improveaccelerator utilization efficiencyVSAvoidjob execution latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The orchestrator server predicts future job requirements and pre-configures accelerators by registering bit-streams in advance. This allows the system to maintain high accelerator utilization while eliminating execution latency, as accelerators are proactively prepared with the necessary bit-streams before jobs are actually submitted.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts its pre-registration strategy based on predicted job patterns and actual workload characteristics. By making the pre-registration process adaptive and flexible, the system optimizes both accelerator utilization and execution latency reduction, ensuring that resources are prepared efficiently without waste.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP3982273A1Technologies for pre-configuring accelerators by predicting bit-streams
Publication Date: 2022.04.13 INTEL CORP
  • EP3982273A1 patent drawingFigure 1
  • EP3982273A1 patent drawingFigure 2
  • EP3982273A1 patent drawingFigure 3

AI summary

Technologies for pre-configuring accelerators by predicting bit-streams include communication circuitry and a compute device. The compute device includes a compute engine to determine one or more bit-streams registered on each accelerator of multiple accelerators. The compute engine is further to predict a next job to be requested for acceleration from an application of at least one compute sled of multiple compute sleds, predict a bit-stream from a bit-stream library that is to execute the predicted next job requested to be accelerated, and determine whether the predicted bit-stream is already registered on one of the accelerators. In response to a determination that the predicted bit-stream is not registered on one of the accelerators, the compute engine is to select an accelerator from the plurality of accelerators that satisfies characteristics of the predicted bit-stream and register the predicted bit-stream on the determined accelerator.