Accelerator Card Data Transmission Path for Distributed Database Latency

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Solution Overview

Problem

Current technologies fail to effectively reduce communication latency between accelerator cards in a distributed database environment, as existing interface protocols like CXL and RDMA primarily address intra-node or inter-node communication, leaving cross-node communication latency unresolved.

Innovation Solution

The method involves interconnecting high-speed interfaces of accelerator cards to form a data transmission path, allowing accelerator cards to detect cache hits, fetch data from cache or remote nodes, and manage memory registration and queue operations using RDMA protocol, ensuring cache coherency and efficient data transmission across nodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is transmitted through PCle interface and NIC for cross-node communication, then data can be transmitted between nodes, but communication latency is significantly increased

Engineering Contradiction:
Improvedata transmission capabilityVSAvoidcommunication latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent introduces an intermediary data transmission path that directly connects accelerator cards across nodes, bypassing the traditional PCle-NIC route. This intermediary path reduces communication latency by eliminating unnecessary intermediate components while maintaining reliable data transmission between distributed database nodes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the data transmission path by separating accelerator card-to-accelerator card communication from CPU-to-CPU communication. By creating a dedicated high-speed transmission path for accelerator cards that operates independently from the traditional PCle interface, the system achieves lower latency for data-intensive operations without affecting overall system reliability.

Inventive Principle:
Principle #1Segmentation

2Loss of time

If CXL protocol is used to reduce intra-node latency, then accelerator card to CPU communication is improved, but cross-node communication latency remains unresolved

Engineering Contradiction:
Improveintra-node communication latencyVSAvoidcross-node communication capability
Core Design Contradiction:
Loss of timeVSAdaptability or versatility

Solution Approach 1:

The patent creates a universal data transmission mechanism that handles both intra-node and cross-node communications through a unified high-speed path. The data transmission path is designed to be multi-functional, supporting various database operations (scan, insert, update, delete) and communication scenarios (intra-node and cross-node) without requiring separate protocols, thereby achieving both low latency and broad adaptability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Loss of time

If RDMA is used for direct memory access, then inter-node access latency is reduced, but intra-node accelerator card latency is not addressed

Engineering Contradiction:
Improveinter-node access latencyVSAvoidintra-node processing efficiency
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent merges the advantages of RDMA (bypassing OS and CPU for direct memory access) with a dedicated high-speed transmission path for accelerator cards. By combining direct memory access capability with accelerator card-specific optimization, the system simultaneously reduces inter-node access latency and intra-node processing latency, achieving comprehensive performance improvement.

Inventive Principle:
Principle #5Merging (Combining)

4Power

If accelerator cards are deployed in distributed database, then processing power is increased, but communication latency between accelerator cards increases

Engineering Contradiction:
Improveprocessing powerVSAvoidcross-node communication latency
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The patent adds a new dimension to the communication architecture by creating a separate high-speed transmission dimension for accelerator cards. Instead of relying on the traditional CPU-centric communication path, the system establishes a parallel communication channel that operates at a different dimensional level, enabling direct accelerator card-to-accelerator card communication with minimal latency while preserving increased processing power from distributed accelerator deployment.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12147429B2Method and device of data transmission
Publication Date: 2024.11.19 HEFEI SWAYCHIP INFORMATION TECH INC
  • US12147429B2 patent drawing
  • US12147429B2 patent drawing
  • US12147429B2 patent drawing

AI summary

A method and device of data transmission, applied to a distributed database is provided including a plurality of nodes, with accelerator cards provided in at least two of the nodes, the high-speed interfaces of each the accelerator card is interconnected to form a data transmission path, the method including: when the accelerator card receives a database operation command from the CPU of the node requesting access to the target data, generating a data request based on the get data operation or the modify data operation; the accelerator card detects hit the target data in the cache based on the data request, the accelerator card fetches the target data from the cache; otherwise the accelerator card sends a data request message corresponding to the data request to a distant destination node via the data transmission path, and obtains the target data based on the data packet returned from the destination node.