Hardware Accelerator Offloads Checkpointing to Bypass CPU
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Solution Overview
Problem
High performance computing (HPC) systems face inefficiencies in computational storage due to the need for CPUs to perform check pointing operations and data transfer to SSDs, which consumes computational resources and prolongs interruption times during burst buffering.
Innovation Solution
A hardware accelerator device offloads check pointing operations and data transfer from the CPU by receiving computation data, performing check pointing, storing it in a dedicated buffer memory, and directly transmitting it to SSDs using peer-to-peer DMA, bypassing the CPU.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU performs check pointing operations and data transfer to SSDs during burst buffering, then the computation operation can be halted and restored, but the computation interruption time increases and computational resources are consumed
Solution Approach 1:
The patent extracts the check pointing operation and data transfer function from the CPU by introducing a dedicated hardware accelerator device. This device independently performs compression of computation data and direct data transfer to SSDs, removing these time-consuming tasks from the CPU's workload and enabling parallel execution of computation and storage operations
Solution Approach 2:
The hardware accelerator device acts as an intermediary between the CPU and SSDs. It receives computation data from the CPU, performs compression operations, and directly transmits compressed data to SSDs using peer-to-peer DMA, thereby mediating the data flow and enabling efficient burst buffering without CPU involvement in the transfer path
2Productivity
If the CPU is used for data transfer during burst buffering, then data can be stored to SSDs, but the processing load on the CPU increases
Solution Approach 1:
The hardware accelerator device enables self-service by autonomously performing compression and data transfer operations without requiring CPU processing. The device independently manages the entire burst buffering workflow, from receiving raw computation data to storing compressed data on SSDs, thereby freeing CPU resources for their primary computation tasks
Solution Approach 2:
The patent replaces the software-based CPU processing mechanism with a hardware-based accelerator mechanism. This substitution leverages dedicated hardware circuits for compression and DMA controllers for data transfer, providing more efficient and energy-saving operation compared to general-purpose CPU execution
Data Source
AI summary
A method, a hardware accelerator, and a system for performing computational storage utilizing a hardware accelerator device that includes a dedicated buffer memory residing on the hardware accelerator device and is connected to a central processing unit (CPU) via a bus includes receiving, at the hardware accelerator device, computation data from the CPU computing device via the bus, performing, at the hardware accelerator device, a check pointing operation on the received computation data to generate check point data, storing the generated check point data on the dedicated buffer memory residing on the hardware accelerator device, and transmitting the check point data directly from the dedicated buffer memory to a solid state memory connected to the hardware accelerator device via the bus for storage, wherein transmitting the check point data bypasses the CPU.