On-Demand Accelerator Checkpointing for Host-Processor Failure Recovery
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Solution Overview
Problem
As applications become more complex, existing checkpointing methods fail to efficiently manage the differing failure rates of host processors and accelerators, leading to suboptimal checkpoint intervals that can cause resource waste and performance degradation.
Innovation Solution
Implementing a system where the host processor and accelerator have different checkpoint intervals based on their respective failure rates, with the host processor checkpointed at a shorter interval and the accelerator at a longer interval, allowing for on-demand checkpointing of the accelerator memory without involving the host processor, and maintaining accelerator data by not executing operations that change its state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the host processor and accelerator use the same checkpoint interval, then the system is simple to manage, but resource waste occurs due to frequent accelerator checkpointing and performance degradation from unnecessary overhead
Solution Approach 1:
The patent divides the checkpointing system into two independent segments: host processor checkpointing and accelerator checkpointing. Each component has its own checkpoint interval determined by its failure rate, allowing optimized resource usage without requiring complex coordinated management. The host processor checkpoint interval is set based on its failure rate, while the accelerator uses a longer interval based on its own failure characteristics.
Solution Approach 2:
The patent changes the checkpoint interval parameter differently for each component based on their respective failure rates. The host processor uses a shorter checkpoint interval while the accelerator uses a longer interval, optimizing the balance between reliability and resource overhead. This parameter differentiation resolves the contradiction by allowing each component to be checkpointed at the appropriate frequency for its failure characteristics.
2Reliability
If the accelerator is checkpointed frequently at the same interval as the host processor, then reliability is improved, but productivity decreases due to resource waste and performance degradation
Solution Approach 1:
The patent applies different checkpoint interval parameters to the host processor and accelerator based on their respective failure rates. The accelerator, having a lower failure rate, uses a longer checkpoint interval that maintains system reliability while reducing checkpoint overhead and preserving application execution performance.
Solution Approach 2:
The patent applies partial checkpointing to the accelerator by using a longer interval rather than checkpointing at every host processor interval. This partial action is sufficient to maintain reliability given the accelerator's lower failure rate, while avoiding the excessive resource consumption that would occur with frequent checkpointing.
3Productivity
If the accelerator memory is checkpointed without involving the host processor, then productivity is improved by reducing host processor overhead, but device complexity increases due to direct memory access requirements
Solution Approach 1:
The patent implements self-service checkpointing where the accelerator can be checkpointed directly to storage without requiring host processor involvement. The accelerator autonomously manages its own checkpoint operations, transferring its state directly to storage, which improves productivity by eliminating host processor overhead while the direct memory access capability handles the increased architectural requirement.
Data Source
AI summary
An electronic device and method with on-demand accelerator checkpointing are provided. In one general aspect, an electronic device includes a host processor, and an accelerator configured to operate according to instructions transmitted by the host processor to the accelerator, wherein, a memory of the host processor and a memory of the accelerator are respectively checkpointed to a storage at respective different intervals, and in response to a determination that a failure has occurred in the host processor, the memory of the accelerator is checkpointed to the storage.