Accelerator Circuit ISA for Easier Programming and Debugging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current accelerator circuits, while offering high-performance calculations at low costs, are difficult to integrate with the programming interface of CPUs and are challenging to debug due to their specialized hardware nature.
Innovation Solution
A programmable hardware accelerator circuit with a purely functional instruction set architecture (ISA) that allows direct programming and debugging, featuring memory-to-memory instructions, parallel execution, and customizable call instructions, along with a MAC matrix circuit for enhanced neural network computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If accelerator circuits use specialized hardware architecture for high-performance calculations, then computational performance is improved, but ease of operation and debugging capability deteriorates
Solution Approach 1:
The accelerator circuit is equipped with a unified programming interface that allows it to be controlled through standard CPU instruction sets. This enables the specialized hardware to be programmed using general-purpose programming languages and debugged through standard tools, making it as easy to operate as general-purpose processors while maintaining high computational performance through hardware acceleration.
2Ease of operation
If accelerator circuits implement purely functional instruction set architecture with memory-to-memory instructions, then ease of operation is improved, but device complexity increases
Solution Approach 1:
A compiler serves as an intermediary between the high-level programming language and the accelerator circuit's instruction set architecture. The compiler automatically translates memory-to-memory instructions into the specific hardware instructions required by the accelerator, shielding users from the underlying complexity while enabling simple and efficient programming of the sophisticated hardware architecture.
Data Source
AI summary
A system includes a memory to store an input data, an accelerator circuit comprising an input command execution circuit, a neuron matrix command execution circuit, and an output command execution circuit, and a processor, communicatively coupled to the memory and the accelerator circuit, to generate a stream of instructions from a source code targeted the accelerator circuit, each one of the stream of instructions comprising at least one of an input command, a neuron matrix command, or an output command, and issue the stream of instructions to the accelerator circuit for execution by the input command execution circuit, the neuron matrix command execution circuit, and the output command execution circuit.