Accelerator Coherency Quiescing via Dedicated Pause Wiring
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Solution Overview
Problem
Existing mechanisms for data compression and decompression in hardware accelerators face challenges in instantly quiescing from a coherency perspective, leading to performance issues and the need for DMA pinning, which increases overhead and limits responsiveness.
Innovation Solution
A system architecture with an on-chip coherency unit, processing unit, and accelerator connected via dedicated wiring, allowing the accelerator to delay data updates until exclusive coherency state and pause/resume operations based on signaling, enabling instantaneous quiescing without DMA pinning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If existing mechanisms for data compression and decompression in hardware accelerators are used, then data processing speed is improved, but the ability to instantly quiesce from a coherency perspective deteriorates
Solution Approach 1:
The accelerator implements dynamic control of memory operations through pause and resume signals. The coherency unit can dynamically halt memory accesses by asserting a pause signal to the accelerator, allowing the system to transition between active processing and quiescent states. This dynamic control enables the accelerator to respond to coherency requirements while maintaining high processing speeds during active operation.
Solution Approach 2:
A dedicated coherency unit is introduced as an intermediary between the processor and the accelerator. This unit manages memory coherency by interceptating and controlling memory access requests, allowing the accelerator to operate at high speed while the coherency unit ensures proper quiescing by managing the pause/resume signaling and memory access coordination.
2Reliability
If DMA pinning is used to maintain coherency, then memory access reliability is improved, but system overhead increases
Solution Approach 1:
The coherency management functionality is extracted from the accelerator and placed in a dedicated coherency unit. This separation allows the accelerator to focus on high-speed data processing while the coherency unit handles memory access control, eliminating the need for complex DMA pinning mechanisms in the accelerator itself and reducing overall system overhead.
Solution Approach 2:
The coherency unit serves multiple functions: it manages memory coherency, controls pause/resume signaling to the accelerator, and coordinates with the processor. This multi-functional approach replaces the need for specialized DMA pinning mechanisms, reducing system complexity while maintaining reliable memory access control.
3Productivity
If the accelerator continuously processes data, then productivity is improved, but responsiveness to coherency requirements deteriorates
Solution Approach 1:
The accelerator operates in periodic cycles of active processing and quiescent states. During normal operation, it processes data continuously at high throughput. When coherency requirements arise, the coherency unit asserts a pause signal, causing the accelerator to enter a quiescent state. Once coherency is restored, the resume signal triggers the accelerator to return to active processing, maintaining both high productivity and rapid responsiveness to coherency events.
Data Source
AI summary
A system architecture is provided and includes an on-chip coherency unit, a processing unit, an accelerator and dedicated wiring. The processing unit is communicative with the on-chip coherency unit via a first interface. The accelerator is communicative with the on-chip coherency unit via a second interface. The accelerator is configured to be receptive of a request to execute lossless data compression or decompression from the processing unit and to responsively execute the lossless data compression or decompression faster than the processing unit. The processing unit and the accelerator are directly communicative by way of the dedicated wiring.