Hardware Accelerator Command Interface for Asynchronous Virtual Memory Access
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Solution Overview
Problem
Existing data processing systems lack efficient mechanisms for hardware accelerators to perform delegated tasks asynchronously and manage memory access requests using virtual addresses, leading to increased software complexity and performance overhead.
Innovation Solution
The system employs accelerator control interface circuitry to manage hardware accelerators using virtual addresses, reusing the processing circuitry's memory management unit for address translation, and implementing asynchronous task execution, reducing software overhead and configuration complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware accelerators use separate system memory management and require memory pinning, then memory access control is achieved, but software complexity and configuration overhead increase
Solution Approach 1:
The patent merges the accelerator's memory management with the host processor's memory management unit (MMU). The accelerator triggers memory access requests that are routed through the host MMU, allowing virtual address translation to be performed by the existing host MMU infrastructure rather than requiring a separate accelerator MMU. This integration eliminates the need for memory pinning and reduces software complexity while maintaining reliable memory access control.
2Productivity
If hardware accelerators operate asynchronously with delegated tasks, then processing performance improves, but coordination and management overhead increases
Solution Approach 1:
The patent implements a universal command interface that handles both synchronous and asynchronous accelerator operations through a unified mechanism. The processing circuitry executes accelerator commands that can launch asynchronous delegated tasks while using the same control interface and address translation infrastructure. This multi-functional approach allows asynchronous operation to improve processing performance without adding separate coordination mechanisms, thereby reducing management overhead.
3Adaptability or versatility
If hardware accelerators implement their own address translation, then memory access autonomy is achieved, but system resource duplication and complexity increase
Solution Approach 1:
The patent enables the accelerator to autonomously trigger memory access requests using virtual addresses, and the host MMU automatically performs the address translation without requiring accelerator-specific translation logic. The accelerator serves itself by issuing requests through the existing host memory management infrastructure, achieving memory access autonomy while avoiding duplication of MMU resources. This self-service mechanism maintains adaptability while eliminating system resource duplication.
Data Source
AI summary
An apparatus comprises processing circuitry to execute instructions; and accelerator control interface circuitry to exchange control signals with at least one hardware accelerator configurable, based on instructions executed by the processing circuitry, to perform a delegated task. The accelerator control interface circuitry is responsive to an accelerator command launch instruction executed by the processing circuitry, to output a command request to a given hardware accelerator associated with command data for configuring the given hardware accelerator to perform the delegated task. When the accelerator command launch instruction is an accelerator command-with-response launch instruction, the command request comprises a command-with-response request indicating that the given hardware accelerator is to acknowledge the command data. When the accelerator command launch instruction is an accelerator command-without-response launch instruction, the command request comprises a command-without-response request indicating that the given hardware accelerator does not need to acknowledge the command data.