On-Package Accelerator Complex With Shared Scratchpad for RAN Data Flow

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Emerging trends in Beyond 5G wireless networks pose challenges for CPU servers and edge cloud deployments, requiring significant scaling of key performance indicators such as peak data throughput, latency, connection density, and reliability, which existing technologies struggle to address efficiently.

Innovation Solution

An on-package Accelerator Complex (AC) is introduced, comprising a novel IP interface tile and disaggregated IP tiles connected via high-bandwidth Die-to-Die interfaces, utilizing protocols like CXL and UCIe, with scratchpad memory and a data mover to optimize data movement and reduce latency and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If CPU servers and platforms are used for Beyond 5G networks, then general-purpose computing is provided, but performance scaling requirements (10-50× KPIs) cannot be met

Engineering Contradiction:

Improveperformance scaling capabilityVSAvoiddata throughput and latency performance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The system is segmented into multiple specialized accelerator tiles (analog accelerator tile, digital accelerator tile, mixed-signal accelerator tile) that can be independently configured and scaled. Each tile handles specific processing functions, allowing the platform to scale performance by adding or configuring specific tile types rather than relying on general-purpose CPU scaling.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The accelerator complex employs dynamic reconfiguration capabilities where tiles can be programmed and reprogrammed to handle different processing tasks. The interconnect fabric dynamically routes data between tiles and CPU servers based on real-time processing requirements, enabling adaptive performance scaling for varying Beyond 5G workloads.

Inventive Principle:

Principle #15Dynamics

2Device complexity

If traditional IO subsystem architecture is used, then system simplicity is maintained, but data movement bandwidth and latency requirements cannot be satisfied

Engineering Contradiction:

ImproveIO subsystem architectureVSAvoiddata movement bandwidth

Core Design Contradiction:

Device complexityVSSpeed

Solution Approach 1:

The IO subsystem is merged with the accelerator complex through a unified interconnect fabric that directly connects CPU servers to accelerator tiles. This integration eliminates traditional IO bottlenecks by providing direct high-bandwidth paths for data movement between storage devices, network interfaces, and processing tiles without requiring complex hierarchical IO architectures.

Inventive Principle:

Principle #5Merging (Combining)

3Device complexity

If CPU servers handle all processing tasks, then hardware simplicity is maintained, but power consumption and processing efficiency increase

Engineering Contradiction:

Improvehardware configurationVSAvoidpower consumption

Core Design Contradiction:

Device complexityVSUse of energy by moving object

Solution Approach 1:

Processing tasks are extracted from CPU servers and assigned to specialized accelerator tiles based on their specific processing capabilities. Analog accelerator tiles handle analog signal processing, digital tiles handle digital signal processing, and mixed-signal tiles handle both, thereby reducing CPU power consumption by offloading computationally intensive tasks to more energy-efficient specialized hardware.

Inventive Principle:

Principle #2Taking out (Extraction)

4Reliability

If existing technologies are used, then current system compatibility is maintained, but connection density and reliability requirements cannot be met

Engineering Contradiction:

Improveconnection density and reliabilityVSAvoidpeak data throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The accelerator complex provides universal interfaces and protocols that maintain compatibility with existing technologies while enabling enhanced performance. The interconnect fabric supports multiple communication protocols and interface types, allowing the system to meet connection density and reliability requirements for diverse Beyond 5G applications including terrestrial and non-terrestrial networks while maintaining backward compatibility.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12554667B2On-package accelerator complex (AC) for integrating accelerator and IOS for scalable ran and edge cloud solution

Publication Date: 2026.02.17 INTEL CORP

AI summary

Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.