Accelerator Error-Handling APIs for Heterogeneous Processors
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Solution Overview
Problem
Software programmers face challenges in interfacing parallel processing units (PPUs) with accelerators within heterogeneous processors, such as GPUs and deep learning accelerators, due to the complexity and cost involved in these interactions.
Innovation Solution
The implementation of application programming interfaces (APIs) that facilitate the execution of operations by GPUs and accelerators within heterogeneous processors, including stream operation APIs and memory operation APIs, to manage and transfer data between these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software programmers use PPUs with accelerators in heterogeneous processors, then computational performance is improved, but interface complexity and cost increase
Solution Approach 1:
The patent introduces an intermediary layer (API and driver software) between the host CPU and accelerator devices. This intermediary handles complex operations such as memory allocation, data transfer, and error handling, allowing programmers to use simple API calls while the intermediary manages the underlying complexity of interfacing PPUs with accelerators in heterogeneous processors.
2Reliability
If error handling mechanisms are implemented for accelerators, then system reliability is improved, but API complexity increases
Solution Approach 1:
The error handling mechanism operates autonomously through the intermediary layer. When errors occur during accelerator operations, the driver software automatically detects, logs, and handles errors without requiring explicit programmer intervention. The API maintains simplicity by presenting a uniform error handling interface, while the intermediary manages the complex error recovery processes behind the scenes.
Data Source
AI summary
Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more functions to be performed in response to one or more errors from one or more accelerators within a heterogeneous processor.