Hardware Accelerator Exception Replay for Parallel Debugging

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Solution Overview

Problem

Conventional debugging techniques for hardware accelerators require cumbersome breakpoint settings and struggle to identify the location and cause of exceptions due to simultaneous operations of numerous processing elements, with data loss complicating the debugging process.

Innovation Solution

A hardware accelerator with an exception detector and execution controller that detects exceptions, saves re-execution information in integrated memories, and allows for sequential re-execution of computations in debug mode, using the saved information to reproduce the state before the exception and re-execute the command in debug mode to identify and analyze the cause of the exception.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If conventional breakpoint-based debugging is used, then the debugging process can be controlled, but the operation becomes cumbersome and flexible debugging is limited

Engineering Contradiction:
Improvedebugging operationVSAvoidbreakpoint setting complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The system automatically saves re-execution information before an exception occurs, so that when debugging is needed, the state before the exception is already preserved. This eliminates the need for manual breakpoint setting and prepares the debugging environment in advance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The hardware accelerator automatically detects exceptions and initiates re-execution of the computation using saved re-execution information. The system serves itself by automatically preparing debugging information without requiring external intervention or manual breakpoint configuration.

Inventive Principle:
Principle #25Self-service

2Speed

If multiple processing elements operate simultaneously, then computation speed is improved, but it becomes difficult to identify the location and cause of exceptions

Engineering Contradiction:
Improvecomputation speedVSAvoidexception location identification
Core Design Contradiction:
SpeedVSDifficulty of detecting and measuring

Solution Approach 1:

The system divides the simultaneous computation into sequential re-execution steps. By re-executing the computation sequentially after saving re-execution information, the system can identify which processing element caused the exception while maintaining the benefits of parallel computation during normal operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The exception detector provides feedback about where the exception occurred, and the execution controller uses this information to selectively re-execute only the problematic computation sequence. This feedback mechanism allows the system to maintain high-speed parallel computation while being able to trace and identify exceptions when they occur.

Inventive Principle:
Principle #23Feedback

3Productivity

If data is processed at high speed, then productivity is improved, but data loss occurs that complicates the debugging process

Engineering Contradiction:
Improvedata processing speedVSAvoiddata loss
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The system performs preliminary saving of re-execution information before the high-speed computation completes or an exception occurs. This ensures that even though data is processed at high speed, the necessary debugging information is preserved in advance, preventing data loss from complicating the debugging process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system discards the need for manual data preservation during high-speed computation by automatically recovering critical state information through the re-execution information storage. The re-execution information is recovered and used to reproduce the state before exceptions, eliminating the need for manual data saving during fast processing.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS20260010391A1Hardware accelerator and control method
Publication Date: 2026.01.08 FUJITSU LTD
  • US20260010391A1 patent drawing
  • US20260010391A1 patent drawing
  • US20260010391A1 patent drawing

AI summary

A hardware accelerator having a plurality of processing elements, the hardware accelerator includes: an exception detector that detects an occurrence of an exception during an execution of a computation by the plurality of processing elements, and an execution controller that, in response to the exception detector detecting the exception, causes the plurality of processing elements to sequentially re-execute the computation in which the occurrence of the exception has been detected, using re-execution information that has been used by at least a part of the plurality of processing elements for the execution of the computation and has been saved in a re-execution information storage before the detection of the exception.