Accelerator Memory Access Fault Handling via Shared Address Translation
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Solution Overview
Problem
Existing hardware accelerators in data processing systems face inefficiencies due to the need for separate memory management and address translation mechanisms, leading to increased software complexity and overhead, especially when handling asynchronous tasks.
Innovation Solution
Reusing the memory management circuitry of the processing circuitry for address translation of accelerator-triggered memory access requests, allowing hardware accelerators to operate within the same virtual address space as the processing circuitry, and implementing fault status registers to handle address translation faults asynchronously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate memory management and address translation mechanisms are used for hardware accelerators, then hardware accelerators can operate independently, but software complexity and configuration overhead increase
Solution Approach 1:
The patent merges the memory management and address translation functions from the processing circuitry with the hardware accelerator. The hardware accelerator shares the same memory management unit and address translation mechanisms as the processing circuitry, eliminating the need for separate memory management mechanisms and reducing software complexity while maintaining accelerator independence through virtual address space sharing
Solution Approach 2:
The memory management circuitry is designed to serve multiple functions - it handles memory management for both the processing circuitry and the hardware accelerator simultaneously. This universal approach allows a single memory management unit to perform address translation for accelerator-triggered memory access requests, reducing overall system complexity
2Reliability
If separate system memory management units are used for hardware accelerators, then address translation can be handled, but processing performance decreases due to increased overhead
Solution Approach 1:
By combining the memory management functions into a single shared unit that serves both processing circuitry and hardware accelerator, the system eliminates redundant components and reduces overhead. The unified address translation mechanism processes requests more efficiently without the performance penalties associated with separate memory management units
3Reliability
If hardware accelerators use separate memory management mechanisms, then fault handling can be isolated, but configuration overhead increases especially for short tasks
Solution Approach 1:
The universal memory management circuitry handles fault handling for both processing circuitry and hardware accelerator through a unified mechanism. This approach maintains fault handling capabilities while significantly reducing configuration overhead, as the same memory management structures are reused for accelerator tasks without requiring separate configuration processes
Data Source
AI summary
A hardware accelerator comprises accelerator processing circuitry to perform a delegated task on behalf of a processor; control interface circuitry to exchange control signals with the processor to configure the accelerator processing circuitry to perform the delegated task; fault status register storage to store fault status information, the fault status register storage being readable by the processor based on an accelerator register read request received from the processor via the control interface circuitry; and control circuitry to: detect a fault indication received from the processor via the control interface circuitry indicating that a faulting accelerator-triggered memory access request, issued via the control interface circuitry to the processor and specifying a target virtual address, has encountered an address translation fault; and in response to detecting the fault indication, set fault status information in the fault status register storage to indicate information about the faulting accelerator-triggered memory access request that encountered the address translation fault.