Accelerator Interface Task Queue Management

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Solution Overview

Problem

Current heterogeneous processor systems face inefficiencies due to fixed system memory allocation for accelerator function units (AFUs), requiring context switches that consume resources and leading to unbalanced task distribution among multiple AFUs, which hampers performance.

Innovation Solution

A processing system with a heterogeneous processor acceleration method that includes an accelerator interface to manage task queues in system memory, allowing AFUs to execute tasks without frequent mode switches and utilizing a round-robin method for balanced task distribution among multiple AFUs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If AFU is directly connected to bus and system memory, then memory access is simplified, but available memory space for AFU is fixed and cannot be dynamically allocated

Engineering Contradiction:
Improvememory access simplicityVSAvoidmemory space flexibility
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent introduces an intermediary memory management mechanism between the AFU and system memory. The AFU accesses memory through a controlled interface that mediates between the fixed physical connection and the need for flexible virtual memory allocation, allowing dynamic space management while maintaining access simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If tasks are copied from user space to kernel space for AFU execution, then mode switching is enabled, but context switch operations consume excessive resources

Engineering Contradiction:
Improvemode switching capabilityVSAvoidresource consumption during context switch
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements preliminary action by pre-establishing memory regions and access pathways for AFU task execution. By preparing the execution environment in advance and maintaining persistent memory mappings, the system eliminates the need for repeated context switches and resource-intensive mode transitions during task execution.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If multiple AFUs are arranged in one chip to share among several applications, then hardware resource utilization increases, but task distribution becomes unbalanced without coordination

Engineering Contradiction:
Improvenumber of AFUs per chipVSAvoidtask distribution balance
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent introduces feedback mechanisms for task distribution management. The system monitors and tracks task allocation across multiple AFUs, using this feedback information to dynamically adjust task distribution strategies. This ensures balanced workload allocation while maintaining high hardware resource utilization efficiency.

Inventive Principle:
Principle #23Feedback

4Reliability

If AFU executes tasks in kernel mode, then execution authority is enhanced, but task creation in user mode creates mode transition overhead

Engineering Contradiction:
Improveexecution authorityVSAvoidmode transition time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by preparing task definitions and execution parameters in user mode before the actual execution begins. The system pre-allocates memory regions, establishes execution contexts, and prepares all necessary task metadata, so that when execution starts, the AFU can immediately begin work without time-consuming mode transitions or initialization overhead.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10929187B2Processing system and heterogeneous processor acceleration method
Publication Date: 2021.02.23 VIA ALLIANCE SEMICON CO LTD
  • US10929187B2 patent drawing
  • US10929187B2 patent drawing
  • US10929187B2 patent drawing

AI summary

A processing system includes a core, at least one accelerator function unit (AFU) and an accelerator interface. The core is utilized to develop at least one task. The AFU is utilized to execute the task. The accelerator interface is arranged between the core and the AFU to receive an accelerator interface instruction transmitted by the processing core and instruct the AFU to execute the task according to the accelerator interface instruction.