Accelerator Interface Mechanism for Data Processing Systems
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Solution Overview
Problem
There is a need for an efficient interface mechanism between general-purpose processing cores and accelerators in data processing systems that allows for the off-loading of processing tasks while ensuring memory atomicity, asynchronous execution, and the ability to support multiple accelerators with a single instruction set architecture and application programming interface.
Innovation Solution
The mechanism involves attaching accelerators within a physical address space using process-specific address spaces and enabling out-of-order execution from a host processor, with memory-atomic, asynchronous execution of tasks, and using an input/output model for task-based processing, allowing for the sharing of accelerators between multiple processors and transparent adjustment of atomicity granularity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If accelerators are shared between multiple processors with traditional interface mechanisms, then resource utilization improves, but interface complexity and synchronization overhead increase
Solution Approach 1:
The patent implements a universal accelerator interface that can be shared by multiple processors through a standardized task queue mechanism. The same interface structure handles tasks from different processors, eliminating the need for processor-specific interface implementations. This universal interface reduces overall system complexity while enabling multiple processors to utilize the accelerator resource efficiently.
Solution Approach 2:
The patent introduces a task queue as an intermediary structure between processors and accelerators. This mediator abstracts the complexity of direct processor-accelerator communication, allowing processors to submit tasks asynchronously without direct synchronization with accelerator execution. The task queue manages task scheduling and coordination, reducing interface complexity while maintaining high resource utilization.
2Reliability
If memory atomicity is ensured for accelerator tasks, then data consistency improves, but execution flexibility and throughput decrease
Solution Approach 1:
The patent segments memory access operations into atomic task submission and non-atomic task execution phases. The task queue uses atomic operations for enqueueing tasks to ensure data consistency, while the actual accelerator execution operates independently without requiring continuous atomic protection. This segmentation maintains data consistency where needed while allowing high-speed execution elsewhere.
Solution Approach 2:
The patent implements periodic synchronization points in the accelerator interface where atomicity is enforced at task submission and completion boundaries, while allowing non-atomic, high-speed execution during the intermediate processing phases. This periodic application of atomic operations ensures data consistency at critical points without continuously blocking throughput.
3Productivity
If asynchronous execution is implemented for accelerator tasks, then processor efficiency improves, but synchronization and memory visibility become more complex
Solution Approach 1:
The patent implements an asynchronous task queue system where the accelerator interface automatically handles synchronization and memory visibility without requiring complex processor-side coordination. The task queue structure itself manages the complexity of asynchronous execution, providing self-service synchronization mechanisms that allow processors to efficiently submit and retrieve tasks without implementing complex synchronization logic.
4Adaptability or versatility
If a unified interface mechanism is used for multiple accelerators, then system scalability improves, but the ability to handle accelerator-specific optimizations decreases
Solution Approach 1:
The patent designs a universal accelerator interface that can work with multiple different accelerator types through a standardized task queue mechanism. This universal interface enables system scalability by allowing new accelerators to be added without modifying the core interface structure. The same interface framework handles diverse accelerator types, achieving versatility while maintaining scalability.
Data Source
AI summary
A method and apparatus is provided for processing accelerator instructions in a data processing apparatus, where a block of one or more accelerator instructions is executable on a host processor or on an accelerator device. For an instruction executed on the host processor and referencing a first virtual address, the instruction is issued to an instruction queue of the host processor and executed the instruction by the host processor, the executing including translating, by translation hardware of the host processor, the first virtual address to a first physical address. For an instruction executed on the accelerator device and referencing the first virtual address, the first virtual address is translated, by the translation hardware, to a second physical address and the instruction is sent to the accelerator device referencing the second physical address. An accelerator task may be initiated by writing configuration data to an accelerator job queue.