Hardware Accelerator Interrupt Aggregation for Parallel Processing
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Solution Overview
Problem
As the number of processing cores in hardware accelerators increases, managing interrupt signals becomes complex and time-consuming due to the need for multiple Memory Mapped Input Output (MMIO) requests, leading to underutilization of acceleration capabilities and performance degradation.
Innovation Solution
Implementing a hardware accelerator with circuitry to aggregate interrupt request information from each core engine and write it directly to main memory, allowing the CPU to quickly assess the status of the entire hardware accelerator, reducing the need for multiple MMIO requests and enabling efficient processing of interrupt service requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If multiple MMIO requests are used to read interrupt signals from each processing core, then complete interrupt information can be retrieved, but processing time and CPU load increase significantly
Solution Approach 1:
The patent combines interrupt information from multiple processing cores into a single aggregated data structure that can be read through one MMIO request. Instead of separately reading interrupt registers from each core, the system merges all core interrupt statuses into a unified view, reducing the number of MMIO requests from multiple to a single operation while maintaining complete interrupt information retrieval.
Solution Approach 2:
The patent creates a universal interrupt reading mechanism that can access interrupt information from all processing cores through a single MMIO request. This universal interface allows the CPU to retrieve complete interrupt status across all cores without needing core-specific read operations, thereby reducing processing time while maintaining information completeness.
2Loss of information
If multiple MMIO requests are sent to read interrupt registers, then all interrupt signals can be read, but accelerator cores remain idle and acceleration capabilities are underutilized
Solution Approach 1:
The patent implements preliminary action by having the hardware accelerator proactively aggregate and prepare interrupt information from all cores before the CPU needs to read it. The interrupt information is pre-collected and stored in a ready state, allowing the CPU to retrieve all necessary interrupt data through a single MMIO request without causing accelerator cores to remain idle during the reading process.
Solution Approach 2:
The patent applies self-service by enabling the hardware accelerator to autonomously manage and aggregate its own interrupt information across all cores. The accelerator self-collects and prepares interrupt status data, eliminating the need for the CPU to initiate multiple separate read operations, thereby preventing accelerator idle time while ensuring complete interrupt detection.
3Loss of information
If interrupt information is read from each core separately, then complete status can be obtained, but the number of MMIO requests increases with the number of cores
Solution Approach 1:
The patent merges interrupt status information from all processing cores into a single aggregated data structure. This consolidation allows the system to retrieve complete interrupt status information through one MMIO request instead of requiring separate read requests for each core, thereby reducing the number of MMIO requests from O(n) to O(1) where n is the number of cores, while maintaining full status completeness.
Solution Approach 2:
The patent creates a universal interrupt reading mechanism that serves all processing cores simultaneously through a single MMIO request. This universal interface abstracts the complexity of multiple core readings into one operation, reducing device complexity and the number of MMIO requests while ensuring that complete interrupt status information is obtained across all cores.
Data Source
AI summary
According to embodiments of the present invention, machines, systems, methods and computer program products for processing events including efficiently processing interrupt service requests for peripheral devices, such as hardware accelerators, utilized in parallel processing are provided. For each core engine of a peripheral device, the peripheral device detects whether one or more interrupt signals have been generated. Information associated with the one or more interrupt signals are stored in one or more registers of peripheral device memory, for each core engine. The information is aggregated and stored in a vector of registers in the peripheral device memory, and the aggregated information is written to memory associated with a CPU to enable CPU processing of interrupt requests from each core engine of the peripheral device.