Accelerator Memory Controller Prefetching Coherence Resolution
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Solution Overview
Problem
Current memory access systems experience high latency due to the need for coherence resolution and data prefetching, which delays access to device-attached memory, especially in host bias mode, impacting system performance.
Innovation Solution
A system and method where a device connected to a host processor via a bus includes an accelerator circuit and a controller that operates by sending a message requesting coherence resolution to the host processor and prefetches data from the memory before receiving confirmation of coherence resolution, thereby reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the device waits for coherence resolution confirmation before accessing memory, then memory coherence is maintained, but memory access latency increases
Solution Approach 1:
The device sends a coherence resolution request message to the host processor and simultaneously starts prefetching data from the memory before receiving the coherence resolution confirmation. This preliminary action allows data to be fetched in advance, reducing the time the device needs to wait for both coherence resolution and data availability, thereby reducing memory access latency while maintaining coherence through the protocol.
2Reliability
If the device performs sequential operations (coherence resolution then data prefetching), then operation correctness is ensured, but access speed decreases
Solution Approach 1:
The device overlaps the coherence resolution messaging with the data prefetching operation by sending the coherence request and immediately initiating data prefetching without waiting for confirmation. This continuous useful action ensures that both operations progress simultaneously rather than sequentially, improving data access speed while the coherence protocol ensures operational correctness through proper message handling and confirmation.
Data Source
AI summary
A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.