Hardware Accelerator Messaging Schema Selection
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Solution Overview
Problem
Existing hardware acceleration systems face challenges in efficiently managing message types and precision representations for variables exchanged between hardware accelerators and other components, leading to inflexible and inefficient data communication.
Innovation Solution
A method that determines exchange message types, selects schemas from a schema database, and configures the serial interface of the hardware accelerator to enable flexible message exchange, supporting various precision representations and formats, thereby enabling seamless integration with different programming languages and systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed message type schema is used in hardware acceleration systems, then device complexity is reduced, but adaptability to different precision requirements and message formats deteriorates
Solution Approach 1:
The patent implements dynamic schema selection where the hardware accelerator can choose from multiple pre-configured message type schemas based on runtime requirements. The system maintains a schema database with various precision representations (int8, int16, int32, float16, float32) and selects appropriate schemas dynamically, allowing the fixed hardware structure to adapt to different precision needs without increasing device complexity.
Solution Approach 2:
The system changes parameters by providing multiple predefined schemas with different precision representations and variable counts. Instead of implementing a complex runtime schema generation system, the patent pre-defines schemas with varying parameters (precision, number of variables, variable types) and selects from these during operation, achieving adaptability through parameter variation rather than structural complexity.
2Adaptability or versatility
If multiple precision representations are supported through software, then adaptability improves, but processing speed and efficiency deteriorate
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple message type schemas in a schema database before runtime. Each schema defines specific precision representations, variable counts, and formats. During operation, the system simply selects from these pre-prepared schemas rather than generating or interpreting schemas dynamically, thereby maintaining high processing speed while supporting multiple precision formats.
Solution Approach 2:
The patent replaces the mechanical/software-based dynamic schema generation and interpretation system with a hardware-based schema selection mechanism. The FPGAs or ASICs directly select from pre-defined schemas using hardware logic, substituting complex software processing with efficient hardware selection, thus achieving both multi-precision support and high-speed processing.
3Adaptability or versatility
If custom message schemas are generated for each application, then adaptability improves, but device complexity and configuration overhead increase
Solution Approach 1:
The patent implements universality by creating a schema database that serves multiple applications and precision requirements through a single unified structure. The same hardware accelerator can use different schemas from the database for different applications, eliminating the need for separate custom schema generation logic for each application. This multi-functional schema database reduces device complexity while maintaining adaptability.
Solution Approach 2:
The system uses copying by replicating schema definitions in a centralized database that can be referenced by multiple hardware accelerators and applications. Instead of each application having its own custom schema implementation, the system copies and selects from standardized schema templates, reducing complexity while allowing customization through schema selection.
4Adaptability or versatility
If serialization and deserialization are performed in software, then flexibility improves, but processing throughput deteriorates
Solution Approach 1:
The patent replaces software-based serialization and deserialization with hardware-based implementations in FPGAs or ASICs. The serial interface is directly configured in hardware according to the selected schema, enabling parallel processing and high-speed message exchange. This substitution maintains flexibility through configurable hardware logic while dramatically improving throughput compared to software-based approaches.
Solution Approach 2:
The patent introduces a hardware-based serial interface configuration as an intermediary between the message exchange requirements and the physical communication channel. This hardware intermediary handles the complex serialization and deserialization operations in parallel, acting as a mediator that provides both the flexibility of configurable message formats and the high throughput of hardware-based processing.
Data Source
AI summary
The present disclosure relates to a messaging method for a hardware acceleration system. The method includes determining exchange message types to be exchanged with a hardware accelerator in accordance with an application performed by the hardware acceleration system. The exchange message types indicate a number of variables, and a type of the variables, of the messages. The method also includes selecting schemas from a schema database. The message type schemas indicates a precision representation of variables of messages associated with the schema. The selected schemas correspond to the determined exchange message types. Further, the method includes configuring a serial interface of the hardware accelerator in accordance with the selected schemas, to enable a message exchange including the messages.