Hardware Accelerator Offloads Metadata Duplication in Multi-Controller Storage
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Solution Overview
Problem
In storage systems using write-once data storage methods and multiple controllers, maintaining metadata consistency across controllers while reducing CPU load and improving I/O performance is challenging due to increased CPU load and I/O performance degradation from cache memory duplication and data transfer processing.
Innovation Solution
A storage system architecture that includes multiple storage control units, an accelerator, and a storage drive, where metadata and recovery data are managed to ensure consistency across controllers, with the accelerator offloading metadata duplication and recovery processing from CPU to hardware, enabling roll-forward or roll-back mechanisms to maintain metadata consistency during failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache memory duplication is used to maintain data consistency across controllers, then reliability is improved, but CPU load increases and I/O performance deteriorates
Solution Approach 1:
The patent extracts the data transfer processing function from the CPU and assigns it to a dedicated hardware component (sequencer). This separation allows the CPU to focus on higher-level control tasks while the sequencer handles the repetitive data copying operations, thereby reducing CPU load and improving I/O performance while maintaining cache memory duplication for reliability
Solution Approach 2:
The patent introduces a sequencer as an intermediary hardware component between the CPU and cache memories. This sequencer mediates the data transfer process by automatically copying data between cache memories of multiple controllers, reducing the need for CPU intervention in routine data duplication tasks
2Reliability
If data transfer processing is performed by CPU, then data consistency is maintained, but CPU load increases
Solution Approach 1:
The patent extracts the data transfer processing function from the CPU and assigns it to a dedicated hardware component (sequencer). This separation allows the CPU to focus on higher-level control tasks while the sequencer handles the repetitive data copying operations, thereby reducing CPU load and improving I/O performance while maintaining cache memory duplication for reliability
Solution Approach 2:
The sequencer is designed to autonomously perform data transfer operations between cache memories without requiring continuous CPU intervention. The hardware component self-manages the data consistency maintenance task, freeing the CPU from this routine workload
3Reliability
If metadata duplication is performed across multiple controllers, then data consistency is maintained, but processing time increases
Solution Approach 1:
The patent implements a mechanism where the sequencer pre-performs metadata duplication to cache memories before actual data writing operations. By anticipating and executing metadata updates in advance, the system reduces the critical path delay during data write operations and maintains consistency without adding significant processing overhead
Data Source
AI summary
Provided is a storage system including a plurality of controllers. The storage system adopts a write-once data storage system and can implement high Input/Output (I/O) processing performance while ensuring data consistency when a failure occurs. Before metadata duplication, recovery data including information necessary for performing roll forward or roll back is stored in each controller, and then the metadata duplication is performed. A recovery data storage processing and the metadata duplication are offloaded to a hardware accelerator.