Accelerator Mode Switching for Side Channel Security

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current data processing systems face challenges in securely processing protected content on electronic devices, particularly when accelerators like GPUs operate under non-trusted operating systems, as they may leak side channel information that can be exploited for attacks, even with memory protection measures in place.

Innovation Solution

Implementing a mechanism that allows accelerators to switch between normal and protected modes, restricting side channel information transfer to the host processor during protected mode operations, thereby enhancing security by limiting the exposure of sensitive data and preventing side channel attacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If memory protection measures are implemented to prevent data leakage, then security of protected content is improved, but side channel information can still be leaked through the accelerator

Engineering Contradiction:
Improvesecurity of protected contentVSAvoidside channel information leakage
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The accelerator is divided into two distinct operational modes: protected mode and normal mode. This segmentation allows the system to apply different security policies to different operational contexts, preventing side channel information leakage while maintaining functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The accelerator's operational parameters are dynamically changed based on the mode of operation. In protected mode, specific parameters control the restriction of side channel information transfer to the host processor, while in normal mode, these restrictions are relaxed to allow full functionality.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the accelerator operates in protected mode to restrict side channel information, then security is improved, but the accelerator functionality is limited

Engineering Contradiction:
Improvesecurity of protected contentVSAvoidaccelerator functionality
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The accelerator dynamically switches between protected mode and normal mode based on operational requirements. This dynamic behavior allows the system to adapt the security level and functionality according to the specific task being performed, maximizing both security and versatility.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The accelerator is designed to perform multiple functions through its dual-mode operation. It can securely process protected content in protected mode while maintaining full functionality in normal mode, making it a universal processing unit that adapts to different security requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Ease of operation

If non-trusted programs are allowed to execute on the accelerator, then ease of operation is improved, but security risks increase

Engineering Contradiction:
Improveprogram execution flexibilityVSAvoidsecurity of protected content
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The protected mode acts as an intermediary layer between non-trusted programs and the protected content. Even when non-trusted programs execute on the accelerator, they operate through this intermediary layer that restricts access to side channel information, maintaining security while allowing operational flexibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10719632B2Data processing systems
Publication Date: 2020.07.21 ARM LTD
  • US10719632B2 patent drawing
  • US10719632B2 patent drawing
  • US10719632B2 patent drawing

AI summary

A data processing system includes a host processor that executes an operating system and an accelerator operable to process data under the control of the operating system executing on the host processor. The accelerator can be switched between a normal mode of operation and a protected mode of operation in which the side channel information that can be provided by the accelerator to the host processor is restricted. The data processing system also includes a mechanism for switching the accelerator from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.